Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP Benutzerhandbuch
7.1.1
Hard Decision Data
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Endianness
Figure 71. EN = 0 (Big-Endian Mode) Rate = 3/4
Word
Word
N
N + 1
SP4
SP3
SP2
SP1
SP0
SP9
SP8
SP7
SP6
SP5
0
0
0
A0
X0
0
0
0
0
X1
Word
Word
N + 2
N + 3
SP4
SP3
SP2
SP1
SP0
SP9
SP8
SP7
SP6
SP5
0
0
0
0
X2
0
A3'
0
0
X3
Word
Word
N + 4
N + 5
SP4
SP3
SP2
SP1
SP0
SP9
SP8
SP7
SP6
SP5
0
0
0
0
X4
0
0
0
0
X5
1. OUT_ORDER = 0 EN = 1 (Little-Endian Mode)
OUT_ORDER = 0 results in ordering the hard decision data from 0 to 31 in the 32-bit word output.
Figure 72. Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word
(OUT_ORDER = 0)
63
62
32
31
1
0
Stage
Stage
Stage
Stage
Stage
Stage
N
N - 1
N - 31
N - 32
N - 62
N - 63
Figure 73. Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word
(OUT_ORDER = 0)
63
62
32
31
1
0
Stage
Stage
Stage
Stage
Stage
Stage
N
N - 1
N - 31
N - 32
N - 62
N - 63
2. OUT_ORDER = 1 EN = 1 (Little-Endian Mode)
OUT_ORDER = 1 results in ordering the hard decision data from 32 to 0 in the 32-bit word output.
Figure 74. Source of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word
(OUT_ORDER = 1)
63
62
32
31
1
0
Stage
Stage
Stage
Stage
Stage
Stage
N
N - 1
N - 31
N - 32
N - 62
N - 63
Figure 75. Destination of Endianness Manager - Ordering of Hard Decisions in 32-Bit Word
(OUT_ORDER = 1)
63
62
32
31
1
0
Stage
Stage
Stage
Stage
Stage
Stage
N - 31
N - 30
N
N - 63
N - 33
N - 32
3. OUT_ORDER = 0, EN = 0 (Big-Endian Mode)
Figure 76. Source of Endianness Manager - Trellis Stage Ordering of Hard Decisions in 32-Bit Word
(OUT_ORDER = 0)
63
62
32
31
1
0
Stage
Stage
Stage
Stage
Stage
Stage
N
N - 1
N - 31
N - 32
N - 62
N - 63
SPRUGK1 – March 2009
TMS320C6457 Turbo-Decoder Coprocessor 2
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