CyberpowerPC Microphone MPC603EC Benutzerhandbuch
12
603 Hardware Specifications, REV 2
Preliminary—Subject to Change without Notice
1.3.3 JTAG AC Timing Specifications
Table 8 provides the JTAG AC timing specifications.
Figure 5 provides the JTAG clock input timing diagram.
.
Figure 5. Clock Input Timing Diagram
Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)
Vdd = 3.3
±
5% V dc, GND = 0 V dc
, CL = 50 pF,
0
≤
T
J
≤
105
°
C
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
—
ns
2
TCK clock pulse width measured at 1.4 V
25
—
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
—
ns
1
5
TRST assert time
40
—
ns
6
Boundary-scan input data setup time
6
—
ns
2
7
Boundary-scan input data hold time
27
—
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
25
—
ns
12
TCK to TDO data valid
4
24
ns
13
TCK to TDO high impedance
3
15
ns
Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
TCK
2
2
1
VM
VM
VM
3
3
VM = Midpoint Voltage (1.4 V)