Arm Enterprises GP4020 Benutzerhandbuch
13: Real Time Clock
132
GP4020 GPS Baseband Processor Design Manual
crystal need to be set to ensure that the total loop gain of the oscillator is high enough to guarantee continuous
oscillation under all conditions. Normally this will mean that a loop gain of greater than 1 is needed.
oscillation under all conditions. Normally this will mean that a loop gain of greater than 1 is needed.
A set of equations for calculating C1 and C2 are explained in Section 14.3 "Processor Crystal Oscillator" on page
137.
137.
In the case of this 32.768kHz oscillator, key parameters are:-
Transconductance (gm)
= 9.56uA/V
Output impedance (Zout) = 422M
Ω
Feedback Resistor (Rf)
= 10M
Ω
Using the equations highlighted above, the nominal value for the crystal loading capacitors, C1 and C2 should be
between 5.6pF and 10pF.
between 5.6pF and 10pF.
13.3 Real Time Clock Registers
The Real Time Clock uses four registers. These registers are addressable in the same part of the memory map as
the Peripheral Control Logic Block (PCL).
the Peripheral Control Logic Block (PCL).
The GP4020 Real Time Clock Base Address is 0x4010 1000.
All registers are addressable as 32-bit locations only, but can use sub-memory access.
Address
Offset
Register
Direction
Function
0x000
RTC_PRE
Read/Write
Read Pre-scaler divider value
0x002
RTC_SEC_B
Read
Read Least significant 16-bits of Real Time Clock 24-
bit second counter
bit second counter
0x004
COMP_RTCP
Read/Write
Comparison value for Real Time Clock Pre-scaler
0x006
COMPS_RTCS
Read/Write
Comparison value for 8-bits of Real Time Clock second
counter
& Read only access to Most significant 8-bits of Real
Time Clock 24-bit second counter
counter
& Read only access to Most significant 8-bits of Real
Time Clock 24-bit second counter
Table 13.1 Real Time Clock Register Map
Whilst most of the registers in the GP4020 can be reset by a reset event (POWER_GOOD, RF_PLL_LOCK,
SFT_RESET, NSRESET and Watchdog), there are a couple of areas where a reset will only occur by writing a ‘0’
to bit 0 of the RTC_PRE register:
SFT_RESET, NSRESET and Watchdog), there are a couple of areas where a reset will only occur by writing a ‘0’
to bit 0 of the RTC_PRE register:
1) RTC_PRE[15:1] in the RTC_PRE register;
2) All data bits in register RTC_SEC_B;
3) RTC_SEC_T[7:0] in the COMPS_RTCS register.
13.3.1 RTC Pre-Scaler Divider Register - RTC_PRE -
Memory Offset 0x000
A read of this register returns the number of accumulated RTC clock cycles in the 15-bit RTC pre-scaler, at the time
of access, upto a value of 2
of access, upto a value of 2
15
RTC clock cycles (the pre-scaler will rollover once every second). At the time this
register is accessed, the values in register RTC_SEC_T (part of Register COMPS_RTCS) will be latched.
NOTE: Only a write of '0' to Bit 0 of register RTC_PRE will reset the 15-bit RTC Pre-scaler divider
(RTC_PRE[14:0]) and 24-bit RTC counter (RTC_SEC_B and RTC_SEC_T[7:0]). No other form of reset will
clear these values.
clear these values.