BenutzerhandbuchInhaltsverzeichnisContents3Related Products and Documents5Trademarks5Document References6Document Conventions6INTRODUCTION7GP4020 GPS Baseband Processor Overview7Features7Functional Description8ARM® Processor (ARM7TDMI)9Boot ROM9BµILD Bus9BµILD Serial Input Output (BSIO)912 Channel Correlator (CORR)10DMA Controller (DMAC)10Embedded Micro-Controller Debug Options10Firefly MF1 Micro-Controller core10General Purpose Input Output (GPIO)11Interrupt Controller (INTC)11Memory/Peripheral Controller (MPC)11Peripheral Control Logic (PCL)11Internal SRAM11Real Time Clock (RTC)12System Clock Generator (SCG)12System Services Module (SSM)12System Timer/Counters (SYSTIC)131PPS Timemark Generator (1PPS)13Up Integration Module (UIM)13Universal Asynchronous Receiver Transmitter (UART)13Watchdog (WDOG)13Typical Application14GP4020 PACKAGE AND ELECTRICAL CONNECTIONS17GP4020 100-pin Package Dimensions17GP4020 100-pin Package Electrical Connection Details19ARM7TDMI MICROPROCESSOR25ARM7TDMI Instruction Set Architecture25The Thumb Concept25Thumb’s Advantages25Operating Modes28Register Sets29Low Power ARM7TDMI Sleep Mode30Info on the Undefined Instruction Trap31BOOT ROM33Functional Description33UART Download Data Protocol34The BµILD BUS37Bus Masters37Bus Slaves37Bus Signals38BµILD SERIAL INPUT OUTPUT (BSIO) INTERFACE39Overview39Design Features39Pinout39Architecture40Operational Description40BSIO Frequency Divider45BSIO Slave Select Logic46BSIO Interrupt Control47BSIO Write Buffer and Control Register47BSIO Read Buffer48BSIO Sequencer48BSIO Registers50BSIO Configuration Register - CONFIG - Memory Offset 0x000050BSIO Transfer Register - TRSFR - Memory Offset 0x000451BSIO Mode Register - MODE - Memory Offset 0x000852BSIO Slave Select Registers - SLAVE0, SLAVE1 - Memory Offset (SLAVE0 = 0x0010, SLAVE1 = 0x0014)52BSIO Status Register - BSIO_STAT - Memory Offset - 0x003053BSIO Interrupt Control Register - INTC - Memory Offset - 0x003453BSIO Read/Write Buffer Register - RWBUF - Memory Offset - 0x003854BSIO Control Word Buffer Register - CWBUF - Memory Offset - 0x003C5412-CHANNEL CORRELATOR (CORR)55Introduction55Clock Generator55Timebase Generator55Raw-Timemark Generator57Status Registers57Sample Latches57Address Decoder57Bus Interface57UIM Interface58Tracking Modules58Carrier DCO59Code DCO59Carrier Cycle Counter60C/A Code Generator60Carrier Mixers61Code Mixers61Accumulate and Dump61Code Phase Counter61Code Slew Counter61Epoch Counter61Software Requirements61Software Sequence For Acquisition62Signal Tracking64Data Demodulation64Pseudorange Measurement64Controlling the 12 Channel Correlator65Search Operation65Carrier DCO Programming65Code DCO Programming65Code Generator Programming65Reading the Accumulated Data66Search on Other Code Phases66Data Bit Synchronisation66Reading the Measurement Data66PRESET Mode67Interrupts67Signal Path Delay Introduced by Hardware Signal Processing67Integrated Carrier Phase Measurement6812 Channel Correlator Interface Timing69Write Cycle To Read Cycle Timings70Write Cycle To Write Cycle Timings7012-Channel Correlator Register Maps70Tracking Channel Control Registers71Tracking Channel Data Accumulation Registers72ACCUM_STATUS_A Register - Read Address offset 0x20874ACCUM_STATUS_B Register - Read Address offset 0x20C74ACCUM_STATUS_C Register - Read Address offset 0x20076CHx_ACCUM_RESET Register - Offset <CHx_Accumulate> + 0x0476CHx_CARRIER_CYCLE_COUNTER Register - Offset <CHx_Control> + 0x0877CHx_CARRIER_CYCLE_HIGH Register - Offset <CHx_Control> + 0x1877CHx_CARRIER_CYCLE_LOW Register - Offset <CHx_Control> + 0x0877CHx_CARRIER_DCO_INCR_HIGH Register - Offset <CHx_Control> + 0x0C78CHx_CARRIER_DCO_INCR_LOW Register - Offset <CHx_Control> + 0x1078CHx_CARRIER_DCO_PHASE - Read Address Offset <CHx_Control> + 0x0C78CHx_CODE_DCO_INCR_HIGH Register - Offset <CHx_Control> + 0x1479CHx_CODE_DCO_INCR_LOW Register - Offset <CHx_Control> + 0x1880CHx_CODE_DCO_PHASE Register - Offset <CHx_Control> + 0x1480CHx_CODE_DCO_PRESET_PHASE Register - Offset <CHx_Accum.> + 0x0C80CHx_CODE_PHASE Register - Read Offset <CHx_Control> + 0x0481CHx_CODE_SLEW Register - Read Address Offset <CHx_Control> + 0x0081CHx_EPOCH_CHECK Register - Read Address Offset <CHx_Control> + 0x1C82CHx_EPOCH Register - Read Address Offset <CHx_Control> + 0x1083CHx_EPOCH_COUNT_LOAD Register - Write Offset <CHx_Control> + 0x1C83CHx_I_TRACK Register - Read Address Offset <CHx_Accumulate> + 0x0084CHx_SATCNTL Register - Write Address Offset <CHx_Control> + 0x0084MEAS_STATUS_A Register - Read Address Offset 0x20486MULTI_CHANNEL_SELECT Register - Write Address Offset 0x1F487PROG_ACCUM_INT Register - Write Address Offset 0x1AC88PROG_TIC_HIGH Register - Write Address Offset 0x1B489PROG_TIC_LOW Register - Write Address Offset 0x1BC89RESET_CONTROL Register - Write Address Offset 0x1FC89STATUS Register - Write Address Offset 0x20091SYSTEM_SETUP Register - Write Address Offset 0x1F891TEST_CONTROL Register - Write Address Offset 0x1F092Details of RF Front End Test mode (FE_TEST)93TIMEMARK_CONTROL Register - Write Address Offset 0x1EC95X_DCO_INCR_HIGH Register - Write Address Offset 0x1A495DMA CONTROLLER (DMAC)97Single-Addressed (Fly-by) Data transfers97Set up example of DMAC for a Fly-by transfer from memory to UART TX97Set up example of DMAC for a Fly-by transfer from UART RX to memory101Dual-Addressed (Buffered) Data Transfers103Set up example of DMAC for a Dual-Addressed transfer between two memory locations.103DMAC Triggering105Hardware Triggering105Software Triggering106Cautionary Notes107Packet Transfers in place of Block Transfers107ARM FIQ Promotion107GENERAL PURPOSE INPUT OUTPUT (GPIO) INTERFACE109Introduction109Initialisation111GPIO Registers111GPIO Direction Register – GPIO_DIR - Memory Offse111GPIO Input Register – GPIO_INPUT - Memory Offset112GPIO Output Register – GPIO_OUTPUT - Memory Offse112INTERRUPT CONTROLLER (INTC)113MEMORY PERIPHERAL CONTROLLER (MPC)115Introduction115GP4020 Memory Area 1 Configuration115GP4020 Memory Area 2 Configuration116GP4020 Memory Area 3 Configuration117GP4020 Memory Area 4 Configuration118PERIPHERAL CONTROL LOGIC (PCL)119Introduction119Chip Reset Logic119PLL Enable Logic124Multiplex Logic125Interrupt and Wake-up logic127Chip-wide Power Control modes129Full Power-Down129RF Input and RF Front-end Power-Down130Real Time Clock Crystal Oscillator Cell Disable130System Clock Generator Processor Crystal Oscillator cell Disable130System Clock Generator Phase Locked Loop (PLL) Disable130Peripheral Control Logic Registers130PCL Power Control Register - POW_CNTL - Memory Offset 0x008131PCL Input / Output Control register - IO_REV - Memory Offset 0x00C133PCL Input Read register - IP_READ - Memory Offset 0x00E134PCL Status register - PER_STAT - Memory Offset 0x010134REAL TIME CLOCK (RTC)137Introduction13732kHz Crystal Oscillator137Real Time Clock Registers138RTC Pre-Scaler Divider Register - RTC_PRE - Memory Offset 0x000138RTC Accumulated Seconds - 16 LSBs - RTC_SEC_B - Memory Offset 0x002139RTC Pre-Scaler Comparison Register - COMP_RTCP - Memory Offset 0x004139RTC Second Comparison Register - COMP_RTCS - Memory Offset 0x006139SYSTEM CLOCK GENERATOR (SCG)141Introduction14140MHz Low Level Differential Input142Processor Crystal Oscillator143Using the Processor Clock Oscillator with an external frequency source144Phase Locked Loop (PLL)145Features145PLL Principles and Operation145PLL Programming147System Clock Generator Power Consumption issues151System Clock Generator Registers152SCG Power Control Register - POW_CNTL - Memory Offset 0x008152SCG PLL Control Register - PLL_CNTL - Memory Offset 0x00A1541PPS TIMEMARK GENERATOR155Introduction155Issues To Consider When Aligning Timemark To UTC158UTC Error Budget159Fine-resolution Timemark setting, using TIC period slewing161Functional description161TIC period slewing Configurations for approximate alignment to 1PPS161Timemark setting example 1; TIC period Slewing with No Receiver Clock Offset162Timemark setting example 2; TIC period Slewing with +0.5ppm Receiver Clock Offset163Timemark setting example 3 - TIC period Slewing with +2.5ppm Receiver Clock Offset164Timemark setting example 4 - TIC period Slewing with -2.5ppm Receiver Clock Offset164Fine-resolution Timemark setting, using Timemark Delay Counter165Functional Description165Timemark setting example 5 - Timemark Delay Counter with No Receiver Clock Offset166Timemark setting example 6 - Timemark Delay Counter with +0.5ppm Receiver Clock Offset167Timemark setting example 7 - Timemark Delay Counter with +2.5ppm Receiver Clock Offset167Timemark setting example 8 - Timemark Delay Counter with -2.5ppm Receiver Clock Offset168Data Retention Register1691PPS Timemark Generator Registers1701PPS Timemark STATUS Register - PER_STAT - Memory Offset 0x0101701PPS Timemark Generator TIC Retention Register- TIC_RET - Memory Offset 0x0121711PPS Timemark Generator Delay Counter Register (LSB) - TIM_DEL_LO - Memory Offset 0x0141711PPS Timemark Generator Delay Counter Register (MSB) - TIM_DEL_HI - Memory Offset 0x016172UP-INTEGRATION MODULE (UIM)173UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)175Introduction175Baud Rate Generation175Example Baud Rates176Connections to the B(ILD bus and the Firefly MF1 Core180WATCHDOG TIMER (WDOG)182Design Features182Operational Description183Start-up behaviour183Timer Operation and Watchdog Restart Key183Watchdog Timer ranges184Watchdog Register Map184Watchdog Control / Status Register - CONSTAT - Memory Offset 0x000185Watchdog Primary Counter Reload Register - RELOAD - Memory Offset 0x004185Watchdog Primary Counter Read Register - READ - Memory Offset 0x008185Watchdog Restart Register - RESTART - Memory Offset 0x00C186Watchdog TEST Register - TEST - Memory Offset 0x010186ADDRESS MAPS187GP4020 System Address Map187GP4020 System Address Map Notes187GP4020 Firefly MF1 Address Map189INPUT / OUTPUT PIN CHARACTERISTICS191Pin Types191Input Delays1933.3V Inputs: CLAIO1HD01N, CLAIO1HD03N, CLAIO1NR01N, CLAIP1GD, CLAIP1GU, CLAIP1NR1935V Tolerant Inputs: SCJIO1NR01N, SCJIP1NR194Output Delays194X01 Drive Outputs (x1 Current drive)194Slow L1 outputs: CLAOP01L1.194Normal N outputs (3.3V outputs): CLAIO1HD01N, CLAIO1NR01N, CLAOP01N.195Normal N outputs (5V Tolerant outputs): SCJIO1NR01N.195X03 Drive Outputs (x3 Current drive)195Slow L1 outputs: CLAOP03L1.195Normal N outputs: CLAIO1HD03N, CLAOP03N.196Cell DC Characteristics196TIMING CHARACTERISTICS199Memory Peripheral Controller (MPC) External Read & Write timing parameters with on-chip Wait-state Control199Memory Peripheral Controller (MPC) External Read & Write timing parameters with SWait Control201Direct Memory Access Controller (DMAC) single address transfer timing201External interrupt inputs: Timing for Edge sensitivity mode202External interrupt inputs: Timing for Level sensitivity mode202System Services Module (SSM) Broadcast Diagnostic Timing Diagrams203JTAG interface Timing Diagram203INDEXES205Table of Figures207Table of Data Tables210Größe: 1,99 MBSeiten: 215Language: EnglishHandbuch öffnen
