Arm Enterprises GP4020 Benutzerhandbuch
15: 1PPS Timemark Generator
162
GP4020 GPS Baseband Processor Design Manual
Timemark
Event (s)
TIC
Event
TIC Time (s)
Required
delay (
µs)
TIM_DEL
value
TIM_DEL
_LO
TIM_DEL_
HI
0
0
0
0
40000
0x9C40
0x40
1
10
0.9999965
3.5
40140
0x9CCC
0x40
2
20
1.999993
7
40280
0x9D58
0x40
3
30
2.9999895
10.5
40420
0x9DE4
0x40
100
1000
99.999650
350
54000
0xD2F0
0x40
101
1010
100.9996465
353.5
54140
0xD37C
0x40
182
1820
181.999363
637
65480
0xFFC8
0x40
183
1830
182.9993595
640.5
65620
0x0054
0x41
1000
10000
999.996500
3500
180000
0xBF20
0x42
1001
10010
1000.996497
3503.5
180140
0xBFAC
0x42
10000
100000
9999.965000
35000
1440000
0xF900
0x55
10001
100010
10000.9649965
35003.5
1440140
0xF98C
0x55
28571
285710
28570.9000015
99998.5
4039940
0xA504
0x7D
(SKIP TIC)
285720
28571.899998
100002.0
4040080
0xA590
0x7D
28572
285721
28571.99999765
2.35
40094
0x9C9E
0x40
28573
285731
28572.99999415
5.85
40234
0x9D2A
0x40
Table 15.7 TIC delay calculations for Timemark, using Delay Counter - TIC period with +2.5ppm error
15.5.5 Timemark setting example 8 - Timemark Delay Counter with -2.5ppm Receiver Clock
Offset
In order to show the opposite end of the Receiver Clock Offset tolerance limit, this example indicates what to do in
order to keep Timemark at 1PPS, when the Receiver Clock Offset means that TIC is longer than 100ms in length.
order to keep Timemark at 1PPS, when the Receiver Clock Offset means that TIC is longer than 100ms in length.
For TIC period errors which larger than -1.00ppm due to an offset in the Receiver clock, a similar technique for
adding delays to the RAW_Timemark signal can be applied, but instead of skipping TICs, additional TICs will need
to be introduced. The rate at which additional TICs are added will be proportional to the error in Receiver Clock.
adding delays to the RAW_Timemark signal can be applied, but instead of skipping TICs, additional TICs will need
to be introduced. The rate at which additional TICs are added will be proportional to the error in Receiver Clock.
For example, if the Receiver Clock Offset is noted to be -2.5ppm (+250ns error on TIC period), the actual TIC
period is 0.10000015s. This means that the correction needed at each TIC to align to UTC, is -150ns, and
consequently a delay of -1.5
period is 0.10000015s. This means that the correction needed at each TIC to align to UTC, is -150ns, and
consequently a delay of -1.5
µs is needed at the first Timemark, -3.0µs at the second time-mark, and the same
increment will be subtracted for each Timemark event. If the calculated delay decrements to zero, the next
Timemark will need to be generated after nine TICs, NOT 10, for that Timemark only. This effectively adds an
additional TIC to the Timemark timing. In this instance, the TIC addition will occur once every 660,000 TICs
(approx. every 18.5 hours), as shown in Table 15.8 below.
Timemark will need to be generated after nine TICs, NOT 10, for that Timemark only. This effectively adds an
additional TIC to the Timemark timing. In this instance, the TIC addition will occur once every 660,000 TICs
(approx. every 18.5 hours), as shown in Table 15.8 below.