Arm Enterprises GP4020 Benutzerhandbuch
7: 12-Channel Correlator
GP4020 GPS Baseband Processor Design Manual
49
7 12-CHANNEL
CORRELATOR
(CORR)
7.1 Introduction
The 12-Channel Correlator forms the GPS-specific module of the GP4020 GPS Baseband Processor. It comprises
12 parallel Spread-spectrum signal tracking modules, including Carrier offset mixers, C/A code generators and
mixers, and 1ms Accumulate and Dump registers. Figure 7.1 below shows a block diagram of the correlator. It
consists of the following blocks:
12 parallel Spread-spectrum signal tracking modules, including Carrier offset mixers, C/A code generators and
mixers, and 1ms Accumulate and Dump registers. Figure 7.1 below shows a block diagram of the correlator. It
consists of the following blocks:
7.1.1 Clock
Generator
The Clock Generator block divides the frequency of the 40MHz master clock, which is generated by the System
Clock Generator (refer to section 14), by 6 or 7 to give the internal multi–phase set of clocks. The SAMPCLK pin
(pin 63 (100-pin package)) is an output giving a 4:3 mark–to–space ratio clock at 40 MHz / 7 (= 5·714MHz).
Clock Generator (refer to section 14), by 6 or 7 to give the internal multi–phase set of clocks. The SAMPCLK pin
(pin 63 (100-pin package)) is an output giving a 4:3 mark–to–space ratio clock at 40 MHz / 7 (= 5·714MHz).
7.1.2 Timebase
Generator
The Timebase Generator produces three important timing signals: ACCUM_INT, TIC and MEAS_INT. ACCUM_INT
is an interrupt provided to control data transfer between the correlator accumulators and the microprocessor. It may
be detected by means of the ACCUM_INT output or by reading the ACCUM_STATUS_A register (where bit 15 is a
flag indicating that ACCUM_INT has occurred since the previous read of this register). ACCUM_INT is cleared by
reading ACCUM_STATUS_A. After power–up this interrupt occurs every 505.05
is an interrupt provided to control data transfer between the correlator accumulators and the microprocessor. It may
be detected by means of the ACCUM_INT output or by reading the ACCUM_STATUS_A register (where bit 15 is a
flag indicating that ACCUM_INT has occurred since the previous read of this register). ACCUM_INT is cleared by
reading ACCUM_STATUS_A. After power–up this interrupt occurs every 505.05
µs. The Interrupt period can
subsequently be changed by:
•
toggling the INTERRUPT_PERIOD bit of the SYSTEM_SETUP register, or
•
writing directly to the PROG_ACCUM_INT register.
TIC is an internal signal with a default period of 99999.90
µs. It is used to latch measurement data (Epoch count,
Code phase, Code DCO phase, Carrier DCO phase and Carrier cycle count) of all 12 channels at the same instant.
Its period can subsequently be changed, by writing to the PROG_TIC_HIGH and PROG_TIC_LOW registers, or
toggling the FRONT_END_MODE bit of the SYSTEM_SETUP register.
Its period can subsequently be changed, by writing to the PROG_TIC_HIGH and PROG_TIC_LOW registers, or
toggling the FRONT_END_MODE bit of the SYSTEM_SETUP register.
MEAS_INT is a signal derived from the TIC counter. It may be used by the microprocessor as a software module
switching interrupt either by using the MEAS_INT output or by reading the ACCUM_STATUS_B or
MEAS_STATUS_A registers. MEAS_INT is activated at each TIC and 50 ms before each TIC provided the TIC
period is greater than 50 ms. If the TIC period is less than 50 ms, MEAS_INT is activated only at each TIC. It is
cleared by reading either the ACCUM_STATUS_B or MEAS_STATUS_A register, depending upon the
MEAS_INT_SOURCE bit of the SYSTEM_SETUP register.
switching interrupt either by using the MEAS_INT output or by reading the ACCUM_STATUS_B or
MEAS_STATUS_A registers. MEAS_INT is activated at each TIC and 50 ms before each TIC provided the TIC
period is greater than 50 ms. If the TIC period is less than 50 ms, MEAS_INT is activated only at each TIC. It is
cleared by reading either the ACCUM_STATUS_B or MEAS_STATUS_A register, depending upon the
MEAS_INT_SOURCE bit of the SYSTEM_SETUP register.