Arm Enterprises GP4020 Benutzerhandbuch
7: 12-Channel Correlator
GP4020 GPS Baseband Processor Design Manual
85
7.6.30 STATUS Register -
Write Address Offset 0x200
This register allows the bits on the Accumulation Status registers ACCUM_STATUS_A, ACCUM_STATUS_B, and
ACCUM_STATUS_C to be latched for reading. This could be useful if the Accumulation data is obtained by a
polling routine, rather than an interrupt driven routine.
ACCUM_STATUS_C to be latched for reading. This could be useful if the Accumulation data is obtained by a
polling routine, rather than an interrupt driven routine.
A write operation to this location, irrespective of the data on the bus, latches the state of all status bits contained in
ACCUM_STATUS_A, ACCUM_STATUS_B, and ACCUM_STATUS_C registers. Performing a write to STATUS
prior to reading the status registers ensures reading of stable status values. The latch takes effect within 300ns of
the trailing edge of the write pulse. The active edge transition of the ACCUM_INT signal will also latch the state of
the status bits. It is not necessary to write to STATUS when the status registers are to be read as a response to the
ACCUM_INT signal in an interrupt handling routine. The write to STATUS is required only when the status registers
are read at times that are not synchronised to the interrupts. These two mechanisms are mutually exclusive and
should not be used together – if both are used, a write to STATUS soon after the occurrence of an ACCUM_INT
signal can result in confused readings. To avoid conflict the INTERRUPT_ENABLE in the SYSTEM_SETUP
register should be set to Low if writes to STATUS are to be used.
ACCUM_STATUS_A, ACCUM_STATUS_B, and ACCUM_STATUS_C registers. Performing a write to STATUS
prior to reading the status registers ensures reading of stable status values. The latch takes effect within 300ns of
the trailing edge of the write pulse. The active edge transition of the ACCUM_INT signal will also latch the state of
the status bits. It is not necessary to write to STATUS when the status registers are to be read as a response to the
ACCUM_INT signal in an interrupt handling routine. The write to STATUS is required only when the status registers
are read at times that are not synchronised to the interrupts. These two mechanisms are mutually exclusive and
should not be used together – if both are used, a write to STATUS soon after the occurrence of an ACCUM_INT
signal can result in confused readings. To avoid conflict the INTERRUPT_ENABLE in the SYSTEM_SETUP
register should be set to Low if writes to STATUS are to be used.
If the INTERRUPT_ENABLE bit in SYSTEM_SETUP register is set to Low, the interrupt will not latch the status bits
in the status registers, but a STATUS write access will do so.
in the status registers, but a STATUS write access will do so.
Bit
No.
Mnemonic
Description
Reset
Value
Value
R/W
15:0
Not used
Write–only location provided to allow latching the state of all status bits
in ACCUM_STATUS_A, ACCUM_STATUS_B, and
ACCUM_STATUS_C.
in ACCUM_STATUS_A, ACCUM_STATUS_B, and
ACCUM_STATUS_C.
0
W
Table 7.36 CORR STATUS Register
7.6.31 SYSTEM_SETUP Register -
Write Address Offset 0x1F8
This register is used to set-up some top-level correlator configurations.
Bit
No.
Mnemonic
Description
Reset
Value
Value
R/W
15:11
Not used
-
W
10
MEAS_INT_SOURCE
'1' = MEAS_INT output cleared by a read of MEAS_STATUS_A
register.
'0' = MEAS_INT output cleared by a read of ACCUM_STATUS_B
register.
0
W
9:8
Not used
-
W
7
INTERRUPT_PERIOD
'1' = set default ACCUM_INT period to 854
µ
s.
'0' = set default ACCUM_INT period to 505.05
µ
s.
See description of PROG_ACCUM_INT for more detail.
0
W
6
Reserved
0
W
5
INTERRUPT_ENABLE
Enables and disables correlator-sourced ACCUM_INT and
MEAS_INT interrupt signals.
'1' = enable correlator interrupts.
'0' = disable correlator interrupts
MEAS_INT interrupt signals.
'1' = enable correlator interrupts.
'0' = disable correlator interrupts
0
W
4:1
DISCOP_SELECT[3:0]
Select output signals for DISCOP output:
'1XXX' = 100kHz Square-wave, derived from M_CLK.
'0X1X' = Channel 0 DUMP signal. Indicates when a DUMP event
'1XXX' = 100kHz Square-wave, derived from M_CLK.
'0X1X' = Channel 0 DUMP signal. Indicates when a DUMP event
occurs on channel 0.
'010X' = Raw_Timemark output (NOT 1pps Timemark).
'0001' = High ('1') output
'0000' = Low ('0') output
'0001' = High ('1') output
'0000' = Low ('0') output
0000
W