Digi NS9750 Benutzerhandbuch
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E t h e r n e t C o m m u n i c a t i o n M o d u l e
to be received and written into the receive FIFO, but the frame remains in the FIFO
until the system wakes up. Normal frame filtering is still performed.
until the system wakes up. Normal frame filtering is still performed.
When a qualified frame is inserted into the receive FIFO, the receive packet
processor notifies the system power controller, which performs the wake up
sequence. The frame remains in the receive FIFO until the system wakes up.
processor notifies the system power controller, which performs the wake up
sequence. The frame remains in the receive FIFO until the system wakes up.
Transferring a frame to system memory
The
RX_RD
logic manages the transfer of a frame in the RX_FIFO to system memory.
The transfer is enabled by setting the
ERXDMA
(enable receive DMA) bit in Ethernet
General Control Register #1.
Transferring a frame in the receive FIFO to system memory begins when the
RX_WR
logic notifies the
RX_RD
logic that a good frame is in the receive FIFO. Frames are
transferred to system memory using up to four rings (that is, 1, 2, or 3 rings can also
be used) of buffer descriptors that point to buffers in system memory. The maximum
frame size that each ring can accept is programmable. The first thing the
be used) of buffer descriptors that point to buffers in system memory. The maximum
frame size that each ring can accept is programmable. The first thing the
RX_RD
logic
does, then, is analyze the frame length in the receive status FIFO to determine which
buffer descriptor to use.
buffer descriptor to use.
The
RX_RD
logic goes through the four buffer descriptors looking for the optimum
buffer size. It searches the enabled descriptors starting with A, then B, C, and finally
D; any pools that are full (that is, the F bit is set in the buffer descriptor) are
skipped. The search stops as soon as the logic encounters an available buffer that is
large enough to hold the entire receive frame.
D; any pools that are full (that is, the F bit is set in the buffer descriptor) are
skipped. The search stops as soon as the logic encounters an available buffer that is
large enough to hold the entire receive frame.
The pointers to the first buffer descriptor in each of the four pools are found in the
related Buffer Descriptor Pointer register (RXAPTR, RXBPTR, RXCPTR, RXDPTR).
Pointers to subsequent buffer descriptors are generated by adding an offset of
related Buffer Descriptor Pointer register (RXAPTR, RXBPTR, RXCPTR, RXDPTR).
Pointers to subsequent buffer descriptors are generated by adding an offset of
0x10
from this pointer for each additional buffer used.
Figure 66 shows the format of the buffer descriptors. The current buffer descriptor
for each pool is kept in local registers. The current buffer descriptor registers are
initialized to the buffer descriptors pointed to by the Buffer Descriptor Pointer
registers, by setting the
for each pool is kept in local registers. The current buffer descriptor registers are
initialized to the buffer descriptors pointed to by the Buffer Descriptor Pointer
registers, by setting the
ERXINIT
(enable initialization of
RX
buffer descriptor
registers) bit in Ethernet General Control Register #1. The initialization process is
complete when
complete when
RXINIT
(
RX
initialization complete) is set in the Ethernet General
Status register. At the end of a frame, the next buffer descriptor for the ring just