Digi NS9215 Benutzerhandbuch
. . . . .
M E M O R Y C O N T R O L L E R
Static memory read: Timing and parameters
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213
Burst of zero wait
states with fixed
length
states with fixed
length
This diagram shows a burst of zero wait state reads with the length specified.
Because the length of the burst is known, the chip select can be held asserted
during the whole burst and generate the external transfers before the current AHB
transfer has completed. The first read requires five arbitration cycles; the three
subsequent sequential reads have zero AHB cycles added because the external
transfers are automatically generated.
Because the length of the burst is known, the chip select can be held asserted
during the whole burst and generate the external transfers before the current AHB
transfer has completed. The first read requires five arbitration cycles; the three
subsequent sequential reads have zero AHB cycles added because the external
transfers are automatically generated.
Burst of two wait
states with fixed
length
states with fixed
length
This diagram shows a burst of two wait state reads with the length specified. The
WAITRD
value is used for all transfers in the burst.
Timing parameter
Value
WAITRD
0
WAITOEN
0
WAITPAGE
N/A
WAITWR
N/A
WAITWEN
N/A
WAITTURN
N/A
Timing parameter
Value
WAITRD
0
WAITOEN
0
WAITPAGE
N/A
WAITWR
N/A
WAITWEN
N/A
WAITTURN
N/A
A+C
A
A+4
A+8
D(A)
D(A+4)
D(A+8)
D(A+C)
clk_out
addr
data
cs[n]
st_oe_n