Digi NS9215 Benutzerhandbuch
M E M O R Y C O N T R O L L E R
Asynchronous page mode read
214
Hardware Reference NS9215
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A s y n c h r o n o u s p a g e m o d e r e a d
The memory controller supports asynchronous page mode read of up to four
memory transfers by updating address bits addr[1] and addr[0]. This feature
increases the bandwidth by using a reduced access time for the read accesses that
are in page mode. The first read access takes static wait read and
memory transfers by updating address bits addr[1] and addr[0]. This feature
increases the bandwidth by using a reduced access time for the read accesses that
are in page mode. The first read access takes static wait read and
WAITRD
cycles.
Subsequent read accesses that are in page mode take static wait page and
WAITPAGE
cycles. The chip select and output enable lines are held during the burst, and only
the lower two address bits change between subsequent accesses. At the end of the
burst, the chip select and output enable lines are deasserted together.
the lower two address bits change between subsequent accesses. At the end of the
burst, the chip select and output enable lines are deasserted together.
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A s y n c h r o n o u s p a g e m o d e r e a d : T i m i n g a n d p a r a m e t e r s
This section shows asynchronous page mode read timing diagrams and parameters.
External memory
page mode read
transfer
page mode read
transfer
ThIs diagram shows an external memory page mode read transfer with two initial
wait states and one sequential wait state. The first read requires five AHB
arbitration cycles (plus three wait states); the following (up to 3) sequential
transfers have only one AHB wait state. This gives increased performance over the
equivalent nonpage mode ROM timing.
wait states and one sequential wait state. The first read requires five AHB
arbitration cycles (plus three wait states); the following (up to 3) sequential
transfers have only one AHB wait state. This gives increased performance over the
equivalent nonpage mode ROM timing.
Timing parameter
Value
WAITRD
2
WAITOEN
0
WAITPAGE
N/A
WAITWR
N/A
WAITWEN
N/A
WAITTURN
N/A
A+8
A
A+4
D(A)
D(A+4)
clk_out
addr
data
cs[n]
st_oe_n