Motorola MPC8260 Benutzerhandbuch
23-12
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater
than zero. The buffer pointer can be even or odd and can reside in internal or external
memory.
Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater
than zero. The buffer pointer can be even or odd and can reside in internal or external
memory.
23.12 SCC Transparent Event Register (SCCE)/Mask
Register (SCCM)
When the SCC is in transparent mode, the SCC event register (SCCE) functions as the
transparent event register to report events recognized by the transparent channel and to
generate interrupts. When an event is recognized, the transparent controller sets the
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the
equivalent bits in the transparent mask register (SCCM).
transparent event register to report events recognized by the transparent channel and to
generate interrupts. When an event is recognized, the transparent controller sets the
corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing, the
equivalent bits in the transparent mask register (SCCM).
Event bits are reset by writing ones; writing zeros has no effect. All unmasked bits must be
reset before the CP clears the internal interrupt request to the SIU interrupt controller.
Figure 23-4 shows the event and mask registers.
reset before the CP clears the internal interrupt request to the SIU interrupt controller.
Figure 23-4 shows the event and mask registers.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
GLR
GLT
DCC
Ñ
GRA
Ñ
TXE
Ñ
BSY
TXB
RXB
Reset
0000_0000_0000_0000
R/W
R/W
Address
Figure 23-4. SCC Transparent Event Register (SCCE)/Mask Register (SCCM)
Table 23-9. SCCE/SCCM Field Descriptions
Bit
Name
Description
0Ð2
Ñ
Reserved, should be cleared.
3
GLR
Glitch on Rx. Set when the SCC Þnds a glitch on the receive clock.
4
GLT
Glitch on Tx. Set when the SCC Þnds a glitch on the transmit clock.
5
DCC
DPLL CS changed. Set when the DPLL-generated carrier sense status changes (valid only when the
DPLL is used). Real-time status can be read in SCCS. This is not the CD status mentioned elsewhere.
DPLL is used). Real-time status can be read in SCCS. This is not the CD status mentioned elsewhere.
6Ð7
Ñ
Reserved, should be cleared.
8
GRA
Graceful stop complete. Set when a graceful stop initiated by completes as soon as the transmitter
Þnishes any frame in progress when the
Þnishes any frame in progress when the
GRACEFUL
STOP
TRANSMIT
command was issued. Immediately
if no frame was in progress when the command was issued.
9Ð10 Ñ
Reserved, should be cleared.
11
TXE
Tx error. Set when an error occurs on the transmitter channel.
12
Ñ
Reserved, should be cleared.