Benutzerhandbuch für Motorola MPC8260

Inhaltsverzeichnis

• About This Book

  55
  • Before Using this Manual—Important Note

    55
  • Audience

    55
  • Organization

    56
  • Suggested Reading

    59
  • Conventions

    60
  • Acronyms and Abbreviations

    61
  • PowerPC Architecture Terminology Conventions

    64
• PartI Overview

  67
  • Intended Audience

    67
  • Contents

    67
  • Conventions

    67
  • Acronyms and Abbreviations

    68
  • Chapter1 Overview

    71
    • 1.1 Features

      71
    • 1.2 MPC8260’s Architecture Overview

      74
      • 1.2.1 MPC603e Core

        75
      • 1.2.2 System Interface Unit (SIU)

        76
      • 1.2.3 Communications Processor Module (CPM)

        76
    • 1.3 Software Compatibility Issues

      77
      • 1.3.1 Signals

        77
    • 1.4 Differences between MPC860 and MPC8260

      79
    • 1.5 Serial Protocol Table

      79
    • 1.6 MPC8260 Configurations

      80
      • 1.6.1 Pin Configurations

        80
      • 1.6.2 Serial Performance

        80
    • 1.7 MPC8260 Application Examples

      81
      • 1.7.1 Examples of Communication Systems

        81
        • 1.7.1.1 Remote Access Server

          81
        • 1.7.1.2 Regional Office Router

          82
        • 1.7.1.3 LAN-to-WAN Bridge Router

          83
        • 1.7.1.4 Cellular Base Station

          84
        • 1.7.1.5 Telecommunications Switch Controller

          84
        • 1.7.1.6 SONET Transmission Controller

          85
      • 1.7.2 Bus Configurations

        85
        • 1.7.2.1 Basic System

          85
        • 1.7.2.2 High-Performance Communication

          86
        • 1.7.2.3 High-Performance System Microprocessor

          87
  • Chapter2 PowerPC Processor Core

    89
    • 2.1 Overview

      89
    • 2.2 PowerPC Processor Core Features

      91
      • 2.2.1 Instruction Unit

        93
      • 2.2.2 Instruction Queue and Dispatch Unit

        93
      • 2.2.3 Branch Processing Unit (BPU)

        94
      • 2.2.4 Independent Execution Units

        94
        • 2.2.4.1 Integer Unit (IU)

          94
        • 2.2.4.2 Load/Store Unit (LSU)

          95
        • 2.2.4.3 System Register Unit (SRU)

          95
      • 2.2.5 Completion Unit

        95
      • 2.2.6 Memory Subsystem Support

        96
        • 2.2.6.1 Memory Management Units (MMUs)

          96
        • 2.2.6.2 Cache Units

          96
    • 2.3 Programming Model

      96
      • 2.3.1 Register Set

        96
        • 2.3.1.1 PowerPC Register Set

          97
        • 2.3.1.2 MPC8260-Specific Registers

          99
          • 2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)

            99
          • 2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)

            102
          • 2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2)

            103
          • 2.3.1.2.4 Processor Version Register (PVR)

            104
      • 2.3.2 PowerPC Instruction Set and Addressing Modes

        104
        • 2.3.2.1 Calculating Effective Addresses

          104
        • 2.3.2.2 PowerPC Instruction Set

          104
        • 2.3.2.3 MPC8260 Implementation-Specific Instruction Set

          106
    • 2.4 Cache Implementation

      106
      • 2.4.1 PowerPC Cache Model

        106
      • 2.4.2 MPC8260 Implementation-Specific Cache Implementation

        107
        • 2.4.2.1 Data Cache

          107
        • 2.4.2.2 Instruction Cache

          109
        • 2.4.2.3 Cache Locking

          109
          • 2.4.2.3.1 Entire Cache Locking

            109
          • 2.4.2.3.2 Way Locking

            109
    • 2.5 Exception Model

      110
      • 2.5.1 PowerPC Exception Model

        110
      • 2.5.2 MPC8260 Implementation-Specific Exception Model

        111
      • 2.5.3 Exception Priorities

        114
    • 2.6 Memory Management

      114
      • 2.6.1 PowerPC MMU Model

        115
      • 2.6.2 MPC8260 Implementation-Specific MMU Features

        116
    • 2.7 Instruction Timing

      117
    • 2.8 Differences between the MPC8260’s Core and the PowerPC 603e Microprocessor

      118
  • Chapter3 Memory Map

    121
• PartII Configuration and Reset

  135
  • Audience

    135
  • Contents

    135
  • Suggested Reading

    135
  • Conventions

    136
  • Acronyms and Abbreviations

    136
  • Chapter4 System Interface Unit (SIU)

    139
    • 4.1 System Configuration and Protection

      140
      • 4.1.1 Bus Monitor

        141
      • 4.1.2 Timers Clock

        142
      • 4.1.3 Time Counter (TMCNT)

        142
      • 4.1.4 Periodic Interrupt Timer (PIT)

        143
      • 4.1.5 Software Watchdog Timer

        144
    • 4.2 Interrupt Controller

      145
      • 4.2.1 Interrupt Configuration

        146
      • 4.2.2 Interrupt Source Priorities

        147
        • 4.2.2.1 SCC, FCC, and MCC Relative Priority

          150
        • 4.2.2.2 PIT, TMCNT, and IRQ Relative Priority

          150
        • 4.2.2.3 Highest Priority Interrupt

          151
      • 4.2.3 Masking Interrupt Sources

        151
      • 4.2.4 Interrupt Vector Generation and Calculation

        152
        • 4.2.4.1 Port C External Interrupts

          154
    • 4.3 Programming Model

      155
      • 4.3.1 Interrupt Controller Registers

        155
        • 4.3.1.1 SIU Interrupt Configuration Register (SICR)

          155
        • 4.3.1.2 SIU Interrupt Priority Register (SIPRR)

          156
        • 4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)

          157
        • 4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)

          159
        • 4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)

          160
        • 4.3.1.6 SIU Interrupt Vector Register (SIVEC)

          161
        • 4.3.1.7 SIU External Interrupt Control Register (SIEXR)

          162
      • 4.3.2 System Configuration and Protection Registers

        163
        • 4.3.2.1 Bus Configuration Register (BCR)

          163
        • 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR)

          166
        • 4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)

          166
        • 4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)

          167
        • 4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)

          168
        • 4.3.2.6 SIU Module Configuration Register (SIUMCR)

          169
        • 4.3.2.7 Internal Memory Map Register (IMMR)

          172
        • 4.3.2.8 System Protection Control Register (SYPCR)

          173
        • 4.3.2.9 Software Service Register (SWSR)

          174
        • 4.3.2.10 60x Bus Transfer Error Status and Control Register1 (TESCR1)

          174
        • 4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)

          175
        • 4.3.2.12 Local Bus Transfer Error Status and Control Register1 (L_TESCR1)

          176
        • 4.3.2.13 Local Bus Transfer Error Status and Control Register2 (L_TESCR2)

          177
        • 4.3.2.14 Time Counter Status and Control Register (TMCNTSC)

          178
        • 4.3.2.15 Time Counter Register (TMCNT)

          179
        • 4.3.2.16 Time Counter Alarm Register (TMCNTAL)

          179
      • 4.3.3 Periodic Interrupt Registers

        180
        • 4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)

          180
        • 4.3.3.2 Periodic Interrupt Timer Count Register (PITC)

          181
        • 4.3.3.3 Periodic Interrupt Timer Register (PITR)

          182
    • 4.4 SIU Pin Multiplexing

      182
  • Chapter5 Reset

    185
    • 5.1 Reset Causes

      185
      • 5.1.1 Reset Actions

        186
      • 5.1.2 Power-On Reset Flow

        186
      • 5.1.3 HRESET Flow

        187
      • 5.1.4 SRESET Flow

        187
    • 5.2 Reset Status Register (RSR)

      188
    • 5.3 Reset Mode Register (RMR)

      189
    • 5.4 Reset Configuration

      190
      • 5.4.1 Hard Reset Configuration Word

        192
      • 5.4.2 Hard Reset Configuration Examples

        193
        • 5.4.2.1 Single MPC8260 with Default Configuration

          193
        • 5.4.2.2 Single MPC8260 Configured from Boot EPROM

          194
        • 5.4.2.3 Multiple MPC8260s Configured from Boot EPROM

          194
        • 5.4.2.4 Multiple MPC8260s in a System with No EPROM

          196
• PartIII The Hardware Interface

  197
  • Intended Audience

    197
  • Contents

    197
  • Suggested Reading

    198
  • Conventions

    198
  • Acronyms and Abbreviations

    199
  • Chapter6 External Signals

    203
    • 6.1 Functional Pinout

      203
    • 6.2 Signal Descriptions

      204
  • Chapter7 60x Signals

    215
    • 7.1 Signal Configuration

      216
    • 7.2 Signal Descriptions

      217
      • 7.2.1 Address Bus Arbitration Signals

        217
        • 7.2.1.1 Bus Request (BR)—Output

          217
          • 7.2.1.1.1 Address Bus Request (BR)—Output

            217
          • 7.2.1.1.2 Address Bus Request (BR)—Input

            218
        • 7.2.1.2 Bus Grant (BG)

          218
          • 7.2.1.2.1 Bus Grant (BG)—Input

            218
          • 7.2.1.2.2 Bus Grant (BG)—Output

            219
        • 7.2.1.3 Address Bus Busy (ABB)

          219
          • 7.2.1.3.1 Address Bus Busy (ABB)—Output

            219
          • 7.2.1.3.2 Address Bus Busy (ABB)—Input

            220
      • 7.2.2 Address Transfer Start Signal

        220
        • 7.2.2.1 Transfer Start (TS)

          220
          • 7.2.2.1.1 Transfer Start (TS)—Output

            220
        • 7.2.2.2 Transfer Start (TS)—Input

          220
      • 7.2.3 Address Transfer Signals

        221
        • 7.2.3.1 Address Bus (A[0–31])

          221
          • 7.2.3.1.1 Address Bus (A[0–31])—Output

            221
          • 7.2.3.1.2 Address Bus (A[0–31])—Input

            221
      • 7.2.4 Address Transfer Attribute Signals

        221
        • 7.2.4.1 Transfer Type (TT[0–4])

          222
          • 7.2.4.1.1 Transfer Type (TT[0–4])—Output

            222
          • 7.2.4.1.2 Transfer Type (TT[0–4])—Input

            222
        • 7.2.4.2 Transfer Size (TSIZ[0–3])

          222
        • 7.2.4.3 Transfer Burst (TBST)

          222
        • 7.2.4.4 Global (GBL)

          223
          • 7.2.4.4.1 Global (GBL)—Output

            223
          • 7.2.4.4.2 Global (GBL)—Input

            223
        • 7.2.4.5 Caching-Inhibited (CI)—Output

          223
        • 7.2.4.6 Write-Through (WT)—Output

          223
      • 7.2.5 Address Transfer Termination Signals

        224
        • 7.2.5.1 Address Acknowledge (AACK)

          224
          • 7.2.5.1.1 Address Acknowledge (AACK)—Output

            224
          • 7.2.5.1.2 Address Acknowledge (AACK)—Input

            224
        • 7.2.5.2 Address Retry (ARTRY)

          225
          • 7.2.5.2.1 Address Retry (ARTRY)—Output

            225
          • 7.2.5.2.2 Address Retry (ARTRY)—Input

            225
      • 7.2.6 Data Bus Arbitration Signals

        226
        • 7.2.6.1 Data Bus Grant (DBG)

          226
          • 7.2.6.1.1 Data Bus Grant (DBG)—Input

            226
          • 7.2.6.1.2 Data Bus Grant (DBG)—Output

            226
        • 7.2.6.2 Data Bus Busy (DBB)

          227
          • 7.2.6.2.1 Data Bus Busy (DBB)—Output

            227
          • 7.2.6.2.2 Data Bus Busy (DBB)—Input

            227
      • 7.2.7 Data Transfer Signals

        227
        • 7.2.7.1 Data Bus (D[0–63])

          227
          • 7.2.7.1.1 Data Bus (D[0–63])—Output

            228
          • 7.2.7.1.2 Data Bus (D[0–63])—Input

            228
        • 7.2.7.2 Data Bus Parity (DP[0–7])

          228
          • 7.2.7.2.1 Data Bus Parity (DP[0–7])—Output

            228
          • 7.2.7.2.2 Data Bus Parity (DP[0–7])—Input

            229
      • 7.2.8 Data Transfer Termination Signals

        229
        • 7.2.8.1 Transfer Acknowledge (TA)

          229
          • 7.2.8.1.1 Transfer Acknowledge (TA)—Input

            229
          • 7.2.8.1.2 Transfer Acknowledge (TA)—Output

            230
        • 7.2.8.2 Transfer Error Acknowledge (TEA)

          230
          • 7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input

            230
          • 7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output

            231
        • 7.2.8.3 Partial Data Valid Indication (PSDVAL)

          231
          • 7.2.8.3.1 Partial Data Valid (PSDVAL)—Input

            231
          • 7.2.8.3.2 Partial Data Valid (PSDVAL)—Output

            232
  • Chapter8 The 60x Bus

    233
    • 8.1 Terminology

      233
    • 8.2 Bus Configuration

      234
      • 8.2.1 Single MPC8260 Bus Mode

        234
      • 8.2.2 60x-Compatible Bus Mode

        235
    • 8.3 60x Bus Protocol Overview

      236
      • 8.3.1 Arbitration Phase

        237
      • 8.3.2 Address Pipelining and Split-Bus Transactions

        239
    • 8.4 Address Tenure Operations

      239
      • 8.4.1 Address Arbitration

        239
      • 8.4.2 Address Pipelining

        241
      • 8.4.3 Address Transfer Attribute Signals

        242
        • 8.4.3.1 Transfer Type Signal (TT[0–4]) Encoding

          242
        • 8.4.3.2 Transfer Code Signals TC[0–2]

          245
        • 8.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer

          245
        • 8.4.3.4 Burst Ordering During Data Transfers

          246
        • 8.4.3.5 Effect of Alignment on Data Transfers

          246
        • 8.4.3.6 Effect of Port Size on Data Transfers

          248
        • 8.4.3.7 60x-Compatible Bus Mode—Size Calculation

          251
        • 8.4.3.8 Extended Transfer Mode

          252
      • 8.4.4 Address Transfer Termination

        255
        • 8.4.4.1 Address Retried with ARTRY

          255
        • 8.4.4.2 Address Tenure Timing Configuration

          257
      • 8.4.5 Pipeline Control

        258
    • 8.5 Data Tenure Operations

      258
      • 8.5.1 Data Bus Arbitration

        258
      • 8.5.2 Data Streaming Mode

        259
      • 8.5.3 Data Bus Transfers and Normal Termination

        259
      • 8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration

        260
      • 8.5.5 Port Size Data Bus Transfers and PSDVAL Termination

        260
      • 8.5.6 Data Bus Termination by Assertion of TEA

        262
    • 8.6 Memory Coherency—MEI Protocol

      263
    • 8.7 Processor State Signals

      264
      • 8.7.1 Support for the lwarx/stwcx. Instruction Pair

        265
      • 8.7.2 TLBISYNC Input

        265
    • 8.8 Little-Endian Mode

      265
  • Chapter9 Clocks and Power Control

    267
    • 9.1 Clock Unit

      267
    • 9.2 Clock Configuration

      268
    • 9.3 External Clock Inputs

      271
    • 9.4 Main PLL

      271
      • 9.4.1 PLL Block Diagram

        271
      • 9.4.2 Skew Elimination

        272
    • 9.5 Clock Dividers

      272
    • 9.6 The MPC8260’s Internal Clock Signals

      272
      • 9.6.1 General System Clocks

        273
    • 9.7 PLL Pins

      273
    • 9.8 System Clock Control Register (SCCR)

      274
    • 9.9 System Clock Mode Register (SCMR)

      275
    • 9.10 Basic Power Structure

      276
  • Chapter10 Memory Controller

    277
    • 10.1 Features

      279
    • 10.2 Basic Architecture

      281
      • 10.2.1 Address and Address Space Checking

        284
      • 10.2.2 Page Hit Checking

        285
      • 10.2.3 Error Checking and Correction (ECC)

        285
      • 10.2.4 Parity Generation and Checking

        285
      • 10.2.5 Transfer Error Acknowledge (TEA) Generation

        285
      • 10.2.6 Machine Check Interrupt (MCP) Generation

        285
      • 10.2.7 Data Buffer Controls (BCTLx)

        286
      • 10.2.8 Atomic Bus Operation

        286
      • 10.2.9 Data Pipelining

        286
      • 10.2.10 External Memory Controller Support

        287
      • 10.2.11 External Address Latch Enable Signal (ALE)

        287
      • 10.2.12 ECC/Parity Byte Select (PBSE)

        287
      • 10.2.13 Partial Data Valid Indication (PSDVAL)

        288
    • 10.3 Register Descriptions

      289
      • 10.3.1 Base Registers (BRx)

        290
      • 10.3.2 Option Registers (ORx)

        292
      • 10.3.3 60x SDRAM Mode Register (PSDMR)

        297
      • 10.3.4 Local Bus SDRAM Mode Register (LSDMR)

        300
      • 10.3.5 Machine A/B/C Mode Registers (MxMR)

        302
      • 10.3.6 Memory Data Register (MDR)

        304
      • 10.3.7 Memory Address Register (MAR)

        305
      • 10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)

        306
      • 10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)

        306
      • 10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)

        307
      • 10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)

        308
      • 10.3.12 Memory Refresh Timer Prescaler Register (MPTPR)

        308
      • 10.3.13 60x Bus Error Status and Control Registers (TESCRx)

        309
      • 10.3.14 Local Bus Error Status and Control Registers (L_TESCRx)

        309
    • 10.4 SDRAM Machine

      309
      • 10.4.1 Supported SDRAM Configurations

        311
      • 10.4.2 SDRAM Power-On Initialization

        311
      • 10.4.3 JEDEC-Standard SDRAM Interface Commands

        311
      • 10.4.4 Page-Mode Support and Pipeline Accesses

        312
      • 10.4.5 Bank Interleaving

        312
        • 10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)

          313
      • 10.4.6 SDRAM Device-Specific Parameters

        314
        • 10.4.6.1 Precharge-to-Activate Interval

          314
        • 10.4.6.2 Activate to Read/Write Interval

          315
        • 10.4.6.3 Column Address to First Data Out—CAS Latency

          316
        • 10.4.6.4 Last Data Out to Precharge

          316
        • 10.4.6.5 Last Data In to Precharge—Write Recovery

          317
        • 10.4.6.6 Refresh Recovery Interval (RFRC)

          317
        • 10.4.6.7 External Address Multiplexing Signal

          317
        • 10.4.6.8 External Address and Command Buffers (BUFCMD)

          318
      • 10.4.7 SDRAM Interface Timing

        318
      • 10.4.8 SDRAM Read/Write Transactions

        322
      • 10.4.9 SDRAM Mode-Set Command Timing

        322
      • 10.4.10 SDRAM Refresh

        323
      • 10.4.11 SDRAM Refresh Timing

        323
      • 10.4.12 SDRAM Configuration Examples

        324
        • 10.4.12.1 SDRAM Configuration Example (Page-Based Interleaving)

          324
      • 10.4.13 SDRAM Configuration Example (Bank-Based Interleaving)

        326
    • 10.5 General-Purpose Chip-Select Machine (GPCM)

      327
      • 10.5.1 Timing Configuration

        328
        • 10.5.1.1 Chip-Select Assertion Timing

          329
        • 10.5.1.2 Chip-Select and Write Enable Deassertion Timing

          330
        • 10.5.1.3 Relaxed Timing

          331
        • 10.5.1.4 Output Enable (OE) Timing

          333
        • 10.5.1.5 Programmable Wait State Configuration

          333
        • 10.5.1.6 Extended Hold Time on Read Accesses

          333
      • 10.5.2 External Access Termination

        336
      • 10.5.3 Boot Chip-Select Operation

        337
      • 10.5.4 Differences between MPC8xx’s GPCM and MPC8260’s GPCM

        338
    • 10.6 User-Programmable Machines (UPMs)

      338
      • 10.6.1 Requests

        340
        • 10.6.1.1 Memory Access Requests

          341
        • 10.6.1.2 UPM Refresh Timer Requests

          341
        • 10.6.1.3 Software Requests—run Command

          342
        • 10.6.1.4 Exception Requests

          342
      • 10.6.2 Programming the UPMs

        342
      • 10.6.3 Clock Timing

        343
      • 10.6.4 The RAM Array

        345
        • 10.6.4.1 RAM Words

          346
          • 10.6.4.1.1 Chip-Select Signals (CxTx)

            350
          • 10.6.4.1.2 Byte-Select Signals (BxTx)

            351
          • 10.6.4.1.3 General-Purpose Signals (GxTx, GOx)

            352
          • 10.6.4.1.4 Loop Control

            352
          • 10.6.4.1.5 Repeat Execution of Current RAM Word (REDO)

            352
        • 10.6.4.2 Address Multiplexing

          353
        • 10.6.4.3 Data Valid and Data Sample Control

          353
        • 10.6.4.4 Signals Negation

          354
        • 10.6.4.5 The Wait Mechanism

          354
        • 10.6.4.6 Extended Hold Time on Read Accesses

          355
      • 10.6.5 UPM DRAM Configuration Example

        355
      • 10.6.6 Differences between MPC8xx UPM and MPC8260 UPM

        356
    • 10.7 Memory System Interface Example Using UPM

      357
      • 10.7.0.1 EDO Interface Example

        368
    • 10.8 Handling Devices with Slow or Variable Access Times

      376
      • 10.8.1 Hierarchical Bus Interface Example

        376
      • 10.8.2 Slow Devices Example

        376
    • 10.9 External Master Support (60x-Compatible Mode)

      377
      • 10.9.1 60x-Compatible External Masters

        377
      • 10.9.2 MPC8260-Type External Masters

        377
      • 10.9.3 Extended Controls in 60x-Compatible Mode

        377
      • 10.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode

        378
      • 10.9.5 Address Incrementing for External Bursting Masters

        378
      • 10.9.6 External Masters Timing

        378
        • 10.9.6.1 Example of External Master Using the SDRAM Machine

          380
  • Chapter11 Secondary (L2) Cache Support

    383
    • 11.1 L2 Cache Configurations

      383
      • 11.1.1 Copy-Back Mode

        383
      • 11.1.2 Write-Through Mode

        384
      • 11.1.3 ECC/Parity Mode

        386
    • 11.2 L2 Cache Interface Parameters

      389
    • 11.3 System Requirements When Using the L2 Cache Interface

      389
    • 11.4 L2 Cache Operation

      389
    • 11.5 Timing Example

      390
  • Chapter12 IEEE 1149.1 Test Access Port

    393
    • 12.1 Overview

      393
    • 12.2 TAP Controller

      394
    • 12.3 Boundary Scan Register

      395
    • 12.4 Instruction Register

      420
    • 12.5 MPC8260 Restrictions

      422
    • 12.6 Nonscan Chain Operation

      422
• PartIV Communications Processor Module

  423
  • Intended Audience

    423
  • Contents

    423
  • Suggested Reading

    425
  • Conventions

    426
  • Acronyms and Abbreviations

    426
  • Chapter13 Communications Processor Module Overview

    431
    • 13.1 Features

      431
    • 13.2 MPC8260 Serial Configurations

      433
    • 13.3 Communications Processor (CP)

      434
      • 13.3.1 Features

        434
      • 13.3.2 CP Block Diagram

        434
      • 13.3.3 PowerPC Core Interface

        436
      • 13.3.4 Peripheral Interface

        436
      • 13.3.5 Execution from RAM

        437
      • 13.3.6 RISC Controller Configuration Register (RCCR)

        437
      • 13.3.7 RISC Time-Stamp Control Register (RTSCR)

        439
      • 13.3.8 RISC Time-Stamp Register (RTSR)

        440
      • 13.3.9 RISC Microcode Revision Number

        440
    • 13.4 Command Set

      441
      • 13.4.1 CP Command Register (CPCR)

        441
        • 13.4.1.1 CP Commands

          443
      • 13.4.2 Command Register Example

        445
      • 13.4.3 Command Execution Latency

        445
    • 13.5 Dual-Port RAM

      445
      • 13.5.1 Buffer Descriptors (BDs)

        447
      • 13.5.2 Parameter RAM

        447
    • 13.6 RISC Timer Tables

      448
      • 13.6.1 RISC Timer Table Parameter RAM

        449
      • 13.6.2 RISC Timer Command Register (TM_CMD)

        450
      • 13.6.3 RISC Timer Table Entries

        451
      • 13.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)

        451
      • 13.6.5 set timer Command

        452
      • 13.6.6 RISC Timer Initialization Sequence

        452
      • 13.6.7 RISC Timer Initialization Example

        452
      • 13.6.8 RISC Timer Interrupt Handling

        453
      • 13.6.9 RISC Timer Table Scan Algorithm

        453
      • 13.6.10 Using the RISC Timers to Track CP Loading

        454
  • Chapter14 Serial Interface with Time-Slot Assigner

    455
    • 14.1 Features

      457
    • 14.2 Overview

      458
    • 14.3 Enabling Connections to TSA

      461
    • 14.4 Serial Interface RAM

      462
      • 14.4.1 One Multiplexed Channel with Static Frames

        463
      • 14.4.2 One Multiplexed Channel with Dynamic Frames

        463
      • 14.4.3 Programming SIx RAM Entries

        464
      • 14.4.4 SIx RAM Programming Example

        467
      • 14.4.5 Static and Dynamic Routing

        468
    • 14.5 Serial Interface Registers

      471
      • 14.5.1 SI Global Mode Registers (SIxGMR)

        471
      • 14.5.2 SI Mode Registers (SIxMR)

        471
      • 14.5.3 SIx RAM Shadow Address Registers (SIxRSR)

        477
      • 14.5.4 SI Command Register (SIxCMDR)

        478
      • 14.5.5 SI Status Registers (SIxSTR)

        479
    • 14.6 Serial Interface IDL Interface Support

      479
      • 14.6.1 IDL Interface Example

        480
      • 14.6.2 IDL Interface Programming

        483
    • 14.7 Serial Interface GCI Support

      485
      • 14.7.1 SI GCI Activation/Deactivation Procedure

        487
      • 14.7.2 Serial Interface GCI Programming

        487
        • 14.7.2.1 Normal Mode GCI Programming

          487
        • 14.7.2.2 SCIT Programming

          487
  • Chapter15 CPM Multiplexing

    491
    • 15.1 Features

      492
    • 15.2 Enabling Connections to TSA or NMSI

      493
    • 15.3 NMSI Configuration

      494
    • 15.4 CMX Registers

      496
      • 15.4.1 CMX UTOPIA Address Register (CMXUAR)

        497
      • 15.4.2 CMX SI1 Clock Route Register (CMXSI1CR)

        500
      • 15.4.3 CMX SI2 Clock Route Register (CMXSI2CR)

        501
      • 15.4.4 CMX FCC Clock Route Register (CMXFCR)

        502
      • 15.4.5 CMX SCC Clock Route Register (CMXSCR)

        504
      • 15.4.6 CMX SMC Clock Route Register (CMXSMR)

        507
  • Chapter16 Baud-Rate Generators (BRGs)

    509
    • 16.1 BRG Configuration Registers 1–8 (BRGCx)

      510
    • 16.2 Autobaud Operation on a UART

      512
    • 16.3 UART Baud Rate Examples

      513
  • Chapter17 Timers

    515
    • 17.1 Features

      516
    • 17.2 General-Purpose Timer Units

      516
      • 17.2.1 Cascaded Mode

        517
      • 17.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2)

        518
      • 17.2.3 Timer Mode Registers (TMR1–TMR4)

        520
      • 17.2.4 Timer Reference Registers (TRR1–TRR4)

        521
      • 17.2.5 Timer Capture Registers (TCR1–TCR4)

        522
      • 17.2.6 Timer Counters (TCN1–TCN4)

        522
      • 17.2.7 Timer Event Registers (TER1–TER4)

        522
  • Chapter18 SDMA Channels and IDMA Emulation

    525
    • 18.1 SDMA Bus Arbitration and Bus Transfers

      526
    • 18.2 SDMA Registers

      527
      • 18.2.1 SDMA Status Register (SDSR)

        527
      • 18.2.2 SDMA Mask Register (SDMR)

        528
      • 18.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)

        528
      • 18.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)

        528
    • 18.3 IDMA Emulation

      529
    • 18.4 IDMA Features

      529
    • 18.5 IDMA Transfers

      530
      • 18.5.1 Memory-to-Memory Transfers

        530
        • 18.5.1.1 External Request Mode

          532
        • 18.5.1.2 Normal Mode

          533
      • 18.5.2 Memory to/from Peripheral Transfers

        533
        • 18.5.2.1 Dual-Address Transfers

          534
          • 18.5.2.1.1 Peripheral to Memory

            534
          • 18.5.2.1.2 Memory to Peripheral

            534
        • 18.5.2.2 Single Address (Fly-By) Transfers

          535
          • 18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers

            535
          • 18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers

            535
      • 18.5.3 Controlling 60x Bus Bandwidth

        536
    • 18.6 IDMA Priorities

      536
    • 18.7 IDMA Interface Signals

      536
      • 18.7.1 DREQx and DACKx

        537
        • 18.7.1.1 Level-Sensitive Mode

          537
        • 18.7.1.2 Edge-Sensitive Mode

          537
      • 18.7.2 DONEx

        538
    • 18.8 IDMA Operation

      538
      • 18.8.1 Auto Buffer and Buffer Chaining

        539
      • 18.8.2 IDMAx Parameter RAM

        540
        • 18.8.2.1 DMA Channel Mode (DCM)

          542
        • 18.8.2.2 Data Transfer Types as Programmed in DCM

          544
        • 18.8.2.3 Programming DTS and STS

          544
      • 18.8.3 IDMA Performance

        546
      • 18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)

        546
      • 18.8.5 IDMA BDs

        547
    • 18.9 IDMA Commands

      550
      • 18.9.1 start_idma Command

        550
      • 18.9.2 stop_idma Command

        550
    • 18.10 IDMA Bus Exceptions

      551
      • 18.10.1 Externally Recognizing IDMA Operand Transfers

        551
    • 18.11 Programming the Parallel I/O Registers

      552
    • 18.12 IDMA Programming Examples

      553
      • 18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)—IDMA2

        553
      • 18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)— IDMA3

        554
  • Chapter19 Serial Communications Controllers (SCCs)

    557
    • 19.1 Features

      558
      • 19.1.1 The General SCC Mode Registers (GSMR1–GSMR4)

        559
      • 19.1.2 Protocol-Specific Mode Register (PSMR)

        565
      • 19.1.3 Data Synchronization Register (DSR)

        565
      • 19.1.4 Transmit-on-Demand Register (TODR)

        565
    • 19.2 SCC Buffer Descriptors (BDs)

      566
    • 19.3 SCC Parameter RAM

      569
      • 19.3.1 SCC Base Addresses

        571
      • 19.3.2 Function Code Registers (RFCR and TFCR)

        571
      • 19.3.3 Handling SCC Interrupts

        572
      • 19.3.4 Initializing the SCCs

        573
      • 19.3.5 Controlling SCC Timing with RTS, CTS, and CD

        574
        • 19.3.5.1 Synchronous Protocols

          574
        • 19.3.5.2 Asynchronous Protocols

          577
      • 19.3.6 Digital Phase-Locked Loop (DPLL) Operation

        578
        • 19.3.6.1 Encoding Data with a DPLL

          580
      • 19.3.7 Clock Glitch Detection

        582
      • 19.3.8 Reconfiguring the SCCs

        582
        • 19.3.8.1 General Reconfiguration Sequence for an SCC Transmitter

          582
        • 19.3.8.2 Reset Sequence for an SCC Transmitter

          583
        • 19.3.8.3 General Reconfiguration Sequence for an SCC Receiver

          583
        • 19.3.8.4 Reset Sequence for an SCC Receiver

          583
        • 19.3.8.5 Switching Protocols

          583
      • 19.3.9 Saving Power

        583
  • Chapter20 SCC UART Mode

    585
    • 20.1 Features

      586
    • 20.2 Normal Asynchronous Mode

      587
    • 20.3 Synchronous Mode

      587
    • 20.4 SCC UART Parameter RAM

      588
    • 20.5 Data-Handling Methods: Character- or Message- Based

      589
    • 20.6 Error and Status Reporting

      590
    • 20.7 SCC UART Commands

      590
    • 20.8 Multidrop Systems and Address Recognition

      591
    • 20.9 Receiving Control Characters

      592
    • 20.10 Hunt Mode (Receiver)

      594
    • 20.11 Inserting Control Characters into the Transmit Data Stream

      594
    • 20.12 Sending a Break (Transmitter)

      595
    • 20.13 Sending a Preamble (Transmitter)

      595
    • 20.14 Fractional Stop Bits (Transmitter)

      595
    • 20.15 Handling Errors in the SCC UART Controller

      596
    • 20.16 UART Mode Register (PSMR)

      597
    • 20.17 SCC UART Receive Buffer Descriptor (RxBD)

      599
    • 20.18 SCC UART Transmit Buffer Descriptor (TxBD)

      602
    • 20.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)

      603
    • 20.20 SCC UART Status Register (SCCS)

      605
    • 20.21 SCC UART Programming Example

      606
    • 20.22 S-Records Loader Application

      607
  • Chapter21 SCC HDLC Mode

    609
    • 21.1 SCC HDLC Features

      610
    • 21.2 SCC HDLC Channel Frame Transmission

      610
    • 21.3 SCC HDLC Channel Frame Reception

      611
    • 21.4 SCC HDLC Parameter RAM

      611
    • 21.5 Programming the SCC in HDLC Mode

      613
    • 21.6 SCC HDLC Commands

      613
    • 21.7 Handling Errors in the SCC HDLC Controller

      614
    • 21.8 HDLC Mode Register (PSMR)

      615
    • 21.9 SCC HDLC Receive Buffer Descriptor (RxBD)

      616
    • 21.10 SCC HDLC Transmit Buffer Descriptor (TxBD)

      619
    • 21.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM)

      620
    • 21.12 SCC HDLC Status Register (SCCS)

      622
    • 21.13 SCC HDLC Programming Examples

      622
      • 21.13.1 SCC HDLC Programming Example #1

        623
      • 21.13.2 SCC HDLC Programming Example #2

        624
    • 21.14 HDLC Bus Mode with Collision Detection

      625
      • 21.14.1 HDLC Bus Features

        627
      • 21.14.2 Accessing the HDLC Bus

        627
      • 21.14.3 Increasing Performance

        628
      • 21.14.4 Delayed RTS Mode

        629
      • 21.14.5 Using the Time-Slot Assigner (TSA)

        630
      • 21.14.6 HDLC Bus Protocol Programming

        631
        • 21.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol

          631
        • 21.14.6.2 HDLC Bus Controller Programming Example

          631
  • Chapter22 SCC BISYNC Mode

    633
    • 22.1 Features

      634
    • 22.2 SCC BISYNC Channel Frame Transmission

      634
    • 22.3 SCC BISYNC Channel Frame Reception

      635
    • 22.4 SCC BISYNC Parameter RAM

      635
    • 22.5 SCC BISYNC Commands

      637
    • 22.6 SCC BISYNC Control Character Recognition

      638
    • 22.7 BISYNC SYNC Register (BSYNC)

      639
    • 22.8 SCC BISYNC DLE Register (BDLE)

      640
    • 22.9 Sending and Receiving the Synchronization Sequence

      641
    • 22.10 Handling Errors in the SCC BISYNC

      641
    • 22.11 BISYNC Mode Register (PSMR)

      642
    • 22.12 SCC BISYNC Receive BD (RxBD)

      644
    • 22.13 SCC BISYNC Transmit BD (TxBD)

      646
    • 22.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)

      647
    • 22.15 SCC Status Registers (SCCS)

      648
    • 22.16 Programming the SCC BISYNC Controller

      649
    • 22.17 SCC BISYNC Programming Example

      650
  • Chapter23 SCC Transparent Mode

    653
    • 23.1 Features

      653
    • 23.2 SCC Transparent Channel Frame Transmission Process

      654
    • 23.3 SCC Transparent Channel Frame Reception Process

      654
    • 23.4 Achieving Synchronization in Transparent Mode

      655
      • 23.4.1 Synchronization in NMSI Mode

        655
        • 23.4.1.1 In-Line Synchronization Pattern

          655
        • 23.4.1.2 External Synchronization Signals

          656
          • 23.4.1.2.1 External Synchronization Example

            656
        • 23.4.1.3 Transparent Mode without Explicit Synchronization

          657
      • 23.4.2 Synchronization and the TSA

        657
        • 23.4.2.1 Inline Synchronization Pattern

          658
        • 23.4.2.2 Inherent Synchronization

          658
      • 23.4.3 End of Frame Detection

        658
    • 23.5 CRC Calculation in Transparent Mode

      658
    • 23.6 SCC Transparent Parameter RAM

      658
    • 23.7 SCC Transparent Commands

      659
    • 23.8 Handling Errors in the Transparent Controller

      660
    • 23.9 Transparent Mode and the PSMR

      661
    • 23.10 SCC Transparent Receive Buffer Descriptor (RxBD)

      661
    • 23.11 SCC Transparent Transmit Buffer Descriptor (TxBD)

      662
    • 23.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)

      664
    • 23.13 SCC Status Register in Transparent Mode (SCCS)

      665
    • 23.14 SCC2 Transparent Programming Example

      665
  • Chapter24 SCC Ethernet Mode

    669
    • 24.1 Ethernet on the MPC8260

      670
    • 24.2 Features

      671
    • 24.3 Connecting the MPC8260 to Ethernet

      672
    • 24.4 SCC Ethernet Channel Frame Transmission

      673
    • 24.5 SCC Ethernet Channel Frame Reception

      674
    • 24.6 The Content-Addressable Memory (CAM) Interface

      675
    • 24.7 SCC Ethernet Parameter RAM

      676
    • 24.8 Programming the Ethernet Controller

      678
    • 24.9 SCC Ethernet Commands

      678
    • 24.10 SCC Ethernet Address Recognition

      679
    • 24.11 Hash Table Algorithm

      681
    • 24.12 Interpacket Gap Time

      681
    • 24.13 Handling Collisions

      681
    • 24.14 Internal and External Loopback

      682
    • 24.15 Full-Duplex Ethernet Support

      682
    • 24.16 Handling Errors in the Ethernet Controller

      682
    • 24.17 Ethernet Mode Register (PSMR)

      683
    • 24.18 SCC Ethernet Receive BD

      685
    • 24.19 SCC Ethernet Transmit Buffer Descriptor

      687
    • 24.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)

      689
    • 24.21 SCC Ethernet Programming Example

      691
  • Chapter25 SCC AppleTalk Mode

    693
    • 25.1 Operating the LocalTalk Bus

      693
    • 25.2 Features

      694
    • 25.3 Connecting to AppleTalk

      695
    • 25.4 Programming the SCC in AppleTalk Mode

      695
      • 25.4.1 Programming the GSMR

        695
      • 25.4.2 Programming the PSMR

        696
      • 25.4.3 Programming the TODR

        696
      • 25.4.4 SCC AppleTalk Programming Example

        696
  • Chapter26 Serial Management Controllers (SMCs)

    697
    • 26.1 Features

      698
    • 26.2 Common SMC Settings and Configurations

      699
      • 26.2.1 SMC Mode Registers (SMCMR1/SMCMR2)

        699
      • 26.2.2 SMC Buffer Descriptor Operation

        701
      • 26.2.3 SMC Parameter RAM

        702
        • 26.2.3.1 SMC Function Code Registers (RFCR/TFCR)

          704
      • 26.2.4 Disabling SMCs On-the-Fly

        705
        • 26.2.4.1 SMC Transmitter Full Sequence

          705
        • 26.2.4.2 SMC Transmitter Shortcut Sequence

          705
        • 26.2.4.3 SMC Receiver Full Sequence

          705
        • 26.2.4.4 SMC Receiver Shortcut Sequence

          706
        • 26.2.4.5 Switching Protocols

          706
      • 26.2.5 Saving Power

        706
      • 26.2.6 Handling Interrupts in the SMC

        706
    • 26.3 SMC in UART Mode

      706
      • 26.3.1 Features

        707
      • 26.3.2 SMC UART Channel Transmission Process

        707
      • 26.3.3 SMC UART Channel Reception Process

        708
      • 26.3.4 Programming the SMC UART Controller

        708
      • 26.3.5 SMC UART Transmit and Receive Commands

        708
      • 26.3.6 Sending a Break

        709
      • 26.3.7 Sending a Preamble

        709
      • 26.3.8 Handling Errors in the SMC UART Controller

        709
      • 26.3.9 SMC UART RxBD

        710
      • 26.3.10 SMC UART TxBD

        712
      • 26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)

        714
      • 26.3.12 SMC UART Controller Programming Example

        715
    • 26.4 SMC in Transparent Mode

      716
      • 26.4.1 Features

        717
      • 26.4.2 SMC Transparent Channel Transmission Process

        717
      • 26.4.3 SMC Transparent Channel Reception Process

        718
      • 26.4.4 Using SMSYN for Synchronization

        718
      • 26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization

        719
      • 26.4.6 SMC Transparent Commands

        721
      • 26.4.7 Handling Errors in the SMC Transparent Controller

        721
      • 26.4.8 SMC Transparent RxBD

        722
      • 26.4.9 SMC Transparent TxBD

        723
      • 26.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)

        724
      • 26.4.11 SMC Transparent NMSI Programming Example

        725
    • 26.5 The SMC in GCI Mode

      726
      • 26.5.1 SMC GCI Parameter RAM

        726
      • 26.5.2 Handling the GCI Monitor Channel

        727
        • 26.5.2.1 SMC GCI Monitor Channel Transmission Process

          727
        • 26.5.2.2 SMC GCI Monitor Channel Reception Process

          727
      • 26.5.3 Handling the GCI C/I Channel

        727
        • 26.5.3.1 SMC GCI C/I Channel Transmission Process

          727
        • 26.5.3.2 SMC GCI C/I Channel Reception Process

          727
      • 26.5.4 SMC GCI Commands

        728
      • 26.5.5 SMC GCI Monitor Channel RxBD

        728
      • 26.5.6 SMC GCI Monitor Channel TxBD

        728
      • 26.5.7 SMC GCI C/I Channel RxBD

        729
      • 26.5.8 SMC GCI C/I Channel TxBD

        729
      • 26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)

        730
  • Chapter27 Multi-Channel Controllers (MCCs)

    731
    • 27.1 Features

      731
    • 27.2 MCC Data Structure Organization

      732
    • 27.3 Global MCC Parameters

      733
    • 27.4 Channel Extra Parameters

      735
    • 27.5 Super-Channel Table

      735
    • 27.6 Channel-Specific HDLC Parameters

      738
      • 27.6.1 Internal Transmitter State (TSTATE)

        739
      • 27.6.2 Interrupt Mask (INTMSK)

        739
      • 27.6.3 Channel Mode Register (CHAMR)

        740
      • 27.6.4 Internal Receiver State (RSTATE)

        741
    • 27.7 Channel-Specific Transparent Parameters

      742
      • 27.7.1 Channel Mode Register (CHAMR)—Transparent Mode

        743
    • 27.8 MCC Configuration Registers (MCCFx)

      745
    • 27.9 MCC Commands

      746
    • 27.10 MCC Exceptions

      747
      • 27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM)

        748
        • 27.10.1.1 Interrupt Table Entry

          749
    • 27.11 MCC Buffer Descriptors

      751
      • 27.11.1 Receive Buffer Descriptor (RxBD)

        751
      • 27.11.2 Transmit Buffer Descriptor (TxBD)

        753
    • 27.12 MCC Initialization and Start/Stop Sequence

      754
      • 27.12.1 Single-Channel Initialization

        755
      • 27.12.2 Super Channel Initialization

        756
    • 27.13 MCC Latency and Performance

      756
  • Chapter28 Fast Communications Controllers (FCCs)

    759
    • 28.1 Overview

      760
    • 28.2 General FCC Mode Registers (GFMRx)

      761
    • 28.3 FCC Protocol-Specific Mode Registers (FPSMRx)

      765
    • 28.4 FCC Data Synchronization Registers (FDSRx)

      765
    • 28.5 FCC Transmit-on-Demand Registers (FTODRx)

      765
    • 28.6 FCC Buffer Descriptors

      766
    • 28.7 FCC Parameter RAM

      768
      • 28.7.1 FCC Function Code Registers (FCRx)

        771
    • 28.8 Interrupts from the FCCs

      771
      • 28.8.1 FCC Event Registers (FCCEx)

        772
      • 28.8.2 FCC Mask Registers (FCCMx)

        772
      • 28.8.3 FCC Status Registers (FCCSx)

        772
    • 28.9 FCC Initialization

      772
    • 28.10 FCC Interrupt Handling

      773
    • 28.11 FCC Timing Control

      773
    • 28.12 Disabling the FCCs On-the-Fly

      777
      • 28.12.1 FCC Transmitter Full Sequence

        778
      • 28.12.2 FCC Transmitter Shortcut Sequence

        778
      • 28.12.3 FCC Receiver Full Sequence

        778
      • 28.12.4 FCC Receiver Shortcut Sequence

        779
      • 28.12.5 Switching Protocols

        779
    • 28.13 Saving Power

      779
  • Chapter29 ATM Controller

    781
    • 29.1 Features

      782
    • 29.2 ATM Controller Overview

      784
      • 29.2.1 Transmitter Overview

        785
        • 29.2.1.1 AAL5 Transmitter Overview

          785
        • 29.2.1.2 AAL1 Transmitter Overview

          785
        • 29.2.1.3 AAL0 Transmitter Overview

          786
        • 29.2.1.4 Transmit External Rate and Internal Rate Modes

          786
      • 29.2.2 Receiver Overview

        786
        • 29.2.2.1 AAL5 Receiver Overview

          787
        • 29.2.2.2 AAL1 Receiver Overview

          787
        • 29.2.2.3 AAL0 Receiver Overview

          788
      • 29.2.3 Performance Monitoring

        788
      • 29.2.4 ABR Flow Control

        788
    • 29.3 ATM Pace Control (APC) Unit

      788
      • 29.3.1 APC Modes and ATM Service Types

        788
      • 29.3.2 APC Unit Scheduling Mechanism

        789
      • 29.3.3 Determining the Scheduling Table Size

        790
        • 29.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table

          790
        • 29.3.3.2 Determining the Number of Slots in a Scheduling Table

          791
      • 29.3.4 Determining the Time-Slot Scheduling Rate of a Channel

        791
      • 29.3.5 ATM Traffic Type

        791
        • 29.3.5.1 Peak Cell Rate Traffic Type

          791
        • 29.3.5.2 Determining the PCR Traffic Type Parameters

          791
        • 29.3.5.3 Peak and Sustain Traffic Type (VBR)

          792
          • 29.3.5.3.1 Example for Using VBR Traffic Parameters

            792
          • 29.3.5.3.2 Handling the Cell Loss Priority (CLP)—VBR Type 1 and 2

            793
        • 29.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)

          793
      • 29.3.6 Determining the Priority of an ATM Channel

        793
    • 29.4 VCI/VPI Address Lookup Mechanism

      794
      • 29.4.1 External CAM Lookup

        794
      • 29.4.2 Address Compression

        795
        • 29.4.2.1 VP-Level Address Compression Table (VPLT)

          797
        • 29.4.2.2 VC-Level Address Compression Tables (VCLTs)

          798
      • 29.4.3 Misinserted Cells

        798
      • 29.4.4 Receive Raw Cell Queue

        799
    • 29.5 Available Bit Rate (ABR) Flow Control

      800
      • 29.5.1 The ABR Model

        800
        • 29.5.1.1 ABR Flow Control Source End-System Behavior

          801
        • 29.5.1.2 ABR Flow Control Destination End-System Behavior

          801
        • 29.5.1.3 ABR Flowcharts

          802
      • 29.5.2 RM Cell Structure

        805
        • 29.5.2.1 RM Cell Rate Representation

          806
      • 29.5.3 ABR Flow Control Setup

        807
    • 29.6 OAM Support

      807
      • 29.6.1 ATM-Layer OAM Definitions

        807
      • 29.6.2 Virtual Path (F4) Flow Mechanism

        808
      • 29.6.3 Virtual Channel (F5) Flow Mechanism

        808
      • 29.6.4 Receiving OAM F4 or F5 Cells

        808
      • 29.6.5 Transmitting OAM F4 or F5 Cells

        809
      • 29.6.6 Performance Monitoring

        809
        • 29.6.6.1 Running a Performance Block Test

          810
        • 29.6.6.2 PM Block Monitoring

          810
        • 29.6.6.3 PM Block Generation

          811
        • 29.6.6.4 BRC Performance Calculations

          812
    • 29.7 User-Defined Cells (UDC)

      812
      • 29.7.1 UDC Extended Address Mode (UEAD)

        813
    • 29.8 ATM Layer Statistics

      813
    • 29.9 ATM-to-TDM Interworking

      814
      • 29.9.1 Automatic Data Forwarding

        814
      • 29.9.2 Using Interrupts in Automatic Data Forwarding

        815
      • 29.9.3 Timing Issues

        816
      • 29.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)

        816
      • 29.9.5 Mapping TDM Time Slots to VCs

        816
      • 29.9.6 CAS Support

        816
      • 29.9.7 Trunk Condition

        817
      • 29.9.8 ATM-to-ATM Data Forwarding

        817
    • 29.10 ATM Memory Structure

      817
      • 29.10.1 Parameter RAM

        817
        • 29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)

          820
        • 29.10.1.2 VCI Filtering (VCIF)

          820
        • 29.10.1.3 Global Mode Entry (GMODE)

          821
      • 29.10.2 Connection Tables (RCT, TCT, and TCTE)

        821
        • 29.10.2.1 ATM Channel Code

          822
        • 29.10.2.2 Receive Connection Table (RCT)

          823
          • 29.10.2.2.1 AAL5 Protocol-Specific RCT

            826
          • 29.10.2.2.2 AAL5-ABR Protocol-Specific RCT

            827
          • 29.10.2.2.3 AAL1 Protocol-Specific RCT

            828
          • 29.10.2.2.4 AAL0 Protocol-Specific RCT

            830
        • 29.10.2.3 Transmit Connection Table (TCT)

          831
          • 29.10.2.3.1 AAL5 Protocol-Specific TCT

            834
          • 29.10.2.3.2 AAL1 Protocol-Specific TCT

            834
          • 29.10.2.3.3 AAL0 Protocol-Specific TCT

            835
          • 29.10.2.3.4 VBR Protocol-Specific TCTE

            836
          • 29.10.2.3.5 UBR+ Protocol-Specific TCTE

            837
          • 29.10.2.3.6 ABR Protocol-Specific TCTE

            838
      • 29.10.3 OAM Performance Monitoring Tables

        840
      • 29.10.4 APC Data Structure

        841
        • 29.10.4.1 APC Parameter Tables

          842
        • 29.10.4.2 APC Priority Table

          843
        • 29.10.4.3 APC Scheduling Tables

          843
      • 29.10.5 ATM Controller Buffer Descriptors (BDs)

        844
        • 29.10.5.1 Transmit Buffer Operations

          844
        • 29.10.5.2 Receive Buffers Operation

          845
          • 29.10.5.2.1 Static Buffer Allocation

            845
          • 29.10.5.2.2 Global Buffer Allocation

            846
          • 29.10.5.2.3 Free Buffer Pools

            847
          • 29.10.5.2.4 Free Buffer Pool Parameter Tables

            848
        • 29.10.5.3 ATM Controller Buffers

          849
        • 29.10.5.4 AAL5 RxBD

          849
        • 29.10.5.5 AAL1 RxBD

          851
        • 29.10.5.6 AAL0 RxBD

          852
        • 29.10.5.7 AAL5, AAL1 User-Defined Cell—RxBD Extension

          853
        • 29.10.5.8 AAL5 TxBDs

          854
        • 29.10.5.9 AAL1 TxBDs

          856
        • 29.10.5.10 AAL0 TxBDs

          857
        • 29.10.5.11 AAL5, AAL1 User-Defined Cell—TxBD Extension

          858
      • 29.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)

        858
      • 29.10.7 UNI Statistics Table

        858
    • 29.11 ATM Exceptions

      859
      • 29.11.1 Interrupt Queues

        859
      • 29.11.2 Interrupt Queue Entry

        860
      • 29.11.3 Interrupt Queue Parameter Tables

        861
    • 29.12 The UTOPIA Interface

      862
      • 29.12.1 UTOPIA Interface Master Mode

        862
        • 29.12.1.1 UTOPIA Master Multiple PHY Operation

          863
      • 29.12.2 UTOPIA Interface Slave Mode

        863
        • 29.12.2.1 UTOPIA Slave Multiple PHY Operation

          864
        • 29.12.2.2 UTOPIA Clocking Modes

          864
        • 29.12.2.3 UTOPIA Loop-Back Modes

          865
    • 29.13 ATM Registers

      865
      • 29.13.1 General FCC Mode Register (GFMR)

        865
      • 29.13.2 FCC Protocol-Specific Mode Register (FPSMR)

        865
      • 29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)

        867
      • 29.13.4 FCC Transmit Internal Rate Registers (FTIRRx)

        868
    • 29.14 ATM Transmit Command

      870
    • 29.15 SRTS Generation and Clock Recovery Using External Logic

      871
    • 29.16 Configuring the ATM Controller for Maximum CPM Performance

      872
      • 29.16.1 Using Transmit Internal Rate Mode

        872
      • 29.16.2 APC Configuration

        873
      • 29.16.3 Buffer Configuration

        873
  • Chapter30 Fast Ethernet Controller

    875
    • 30.1 Fast Ethernet on the MPC8260

      876
    • 30.2 Features

      877
    • 30.3 Connecting the MPC8260 to Fast Ethernet

      878
    • 30.4 Ethernet Channel Frame Transmission

      879
    • 30.5 Ethernet Channel Frame Reception

      881
    • 30.6 Flow Control

      882
    • 30.7 CAM Interface

      882
    • 30.8 Ethernet Parameter RAM

      883
    • 30.9 Programming Model

      886
    • 30.10 Ethernet Command Set

      886
    • 30.11 RMON Support

      888
    • 30.12 Ethernet Address Recognition

      889
    • 30.13 Hash Table Algorithm

      891
    • 30.14 Interpacket Gap Time

      892
    • 30.15 Handling Collisions

      892
    • 30.16 Internal and External Loopback

      892
    • 30.17 Ethernet Error-Handling Procedure

      893
    • 30.18 Fast Ethernet Registers

      893
      • 30.18.1 FCC Ethernet Mode Register (FPSMR)

        894
      • 30.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)

        895
    • 30.19 Ethernet RxBDs

      897
    • 30.20 Ethernet TxBDs

      900
  • Chapter31 FCC HDLC Controller

    903
    • 31.1 Key Features

      904
    • 31.2 HDLC Channel Frame Transmission Processing

      904
    • 31.3 HDLC Channel Frame Reception Processing

      905
    • 31.4 HDLC Parameter RAM

      906
    • 31.5 Programming Model

      907
      • 31.5.1 HDLC Command Set

        907
      • 31.5.2 HDLC Error Handling

        908
    • 31.6 HDLC Mode Register (FPSMR)

      909
    • 31.7 HDLC Receive Buffer Descriptor (RxBD)

      911
    • 31.8 HDLC Transmit Buffer Descriptor (TxBD)

      914
    • 31.9 HDLC Event Register (FCCE)/Mask Register (FCCM)

      916
    • 31.10 FCC Status Register (FCCS)

      918
  • Chapter32 FCC Transparent Controller

    921
    • 32.1 Features

      922
    • 32.2 Transparent Channel Operation

      922
    • 32.3 Achieving Synchronization in Transparent Mode

      922
      • 32.3.1 In-Line Synchronization Pattern

        923
      • 32.3.2 External Synchronization Signals

        923
      • 32.3.3 Transparent Synchronization Example

        924
  • Chapter33 Serial Peripheral Interface (SPI)

    925
    • 33.1 Features

      926
    • 33.2 SPI Clocking and Signal Functions

      926
    • 33.3 Configuring the SPI Controller

      927
      • 33.3.1 The SPI as a Master Device

        927
      • 33.3.2 The SPI as a Slave Device

        928
      • 33.3.3 The SPI in Multimaster Operation

        928
    • 33.4 Programming the SPI Registers

      930
      • 33.4.1 SPI Mode Register (SPMODE)

        930
        • 33.4.1.1 SPI Examples with Different SPMODE[LEN] Values

          932
      • 33.4.2 SPI Event/Mask Registers (SPIE/SPIM)

        933
      • 33.4.3 SPI Command Register (SPCOM)

        933
    • 33.5 SPI Parameter RAM

      934
      • 33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)

        936
    • 33.6 SPI Commands

      936
    • 33.7 The SPI Buffer Descriptor (BD) Table

      937
      • 33.7.1 SPI Buffer Descriptors (BDs)

        937
        • 33.7.1.1 SPI Receive BD (RxBD)

          938
        • 33.7.1.2 SPI Transmit BD (TxBD)

          939
    • 33.8 SPI Master Programming Example

      940
    • 33.9 SPI Slave Programming Example

      941
    • 33.10 Handling Interrupts in the SPI

      942
  • Chapter34 I2C Controller

    943
    • 34.1 Features

      944
    • 34.2 I2C Controller Clocking and Signal Functions

      944
    • 34.3 I2C Controller Transfers

      945
      • 34.3.1 I2C Master Write (Slave Read)

        946
      • 34.3.2 I2C Loopback Testing

        946
      • 34.3.3 I2C Master Read (Slave Write)

        946
      • 34.3.4 I2C Multi-Master Considerations

        947
    • 34.4 I2C Registers

      948
      • 34.4.1 I2C Mode Register (I2MOD)

        948
      • 34.4.2 I2C Address Register (I2ADD)

        949
      • 34.4.3 I2C Baud Rate Generator Register (I2BRG)

        949
      • 34.4.4 I2C Event/Mask Registers (I2CER/I2CMR)

        950
      • 34.4.5 I2C Command Register (I2COM)

        950
    • 34.5 I2C Parameter RAM

      951
    • 34.6 I2C Commands

      953
    • 34.7 The I2C Buffer Descriptor (BD) Table

      954
      • 34.7.1 I2C Buffer Descriptors (BDs)

        954
        • 34.7.1.1 I2C Receive Buffer Descriptor (RxBD)

          955
        • 34.7.1.2 I2C Transmit Buffer Descriptor (TxBD)

          956
  • Chapter35 Parallel I/O Ports

    957
    • 35.1 Features

      957
    • 35.2 Port Registers

      958
      • 35.2.1 Port Open-Drain Registers (PODRA–PODRD)

        958
      • 35.2.2 Port Data Registers (PDATA–PDATD)

        958
      • 35.2.3 Port Data Direction Registers (PDIRA–PDIRD)

        959
      • 35.2.4 Port Pin Assignment Register (PPAR)

        960
      • 35.2.5 Port Special Options Registers A–D (PSORA–PSORD)

        960
    • 35.3 Port Block Diagram

      962
    • 35.4 Port Pins Functions

      962
      • 35.4.1 General Purpose I/O Pins

        963
      • 35.4.2 Dedicated Pins

        963
    • 35.5 Ports Tables

      963
    • 35.6 Interrupts from Port C

      975
    • A.1 PowerPC Registers—User Registers

      977
    • A.2 PowerPC Registers—Supervisor Registers

      978
    • A.3 MPC8260-Specific SPRs

      979