Intel 8XC196MC Benutzerhandbuch
4-3
MEMORY PARTITIONS
4.1.4
Special-purpose Memory
Special-purpose memory resides in locations 2000–207FH (Table 4-2). It contains several re-
served memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral
transaction server (PTS) and standard interrupts. Accesses to this address range are directed to
internal memory if EA# is held high and to external memory if EA# is held low. For devices with-
out internal nonvolatile memory, the EA# signal must be tied low. EA# is latched at reset.
served memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral
transaction server (PTS) and standard interrupts. Accesses to this address range are directed to
internal memory if EA# is held high and to external memory if EA# is held low. For devices with-
out internal nonvolatile memory, the EA# signal must be tied low. EA# is latched at reset.
4.1.4.1
Reserved Memory Locations
Several memory locations are reserved for testing or for use in future products. Do not read or
write these locations except to initialize them. The function or contents of these locations may
change in future revisions; software that uses reserved locations may not function properly. Al-
ways initialize reserved locations to the values listed in Table 4-2.
write these locations except to initialize them. The function or contents of these locations may
change in future revisions; software that uses reserved locations may not function properly. Al-
ways initialize reserved locations to the values listed in Table 4-2.
4.1.4.2
Interrupt and PTS Vectors
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. The
peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks. See
Chapter 5, “Standard and PTS Interrupts,” for more information on interrupt and PTS vectors.
peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks. See
Chapter 5, “Standard and PTS Interrupts,” for more information on interrupt and PTS vectors.
Table 4-2. Special-purpose Memory Addresses
Hex Address
Description
207F
205E
Reserved (each byte must contain FFH)
205D
2040
PTS vectors
203F
2030
Upper interrupt vectors
202F
2020
Security key
201F
Reserved (must contain 20H)
201E
Reserved (must contain FFH)
201D
Reserved (must contain 20H)
201C
Reserved (must contain FFH)
201B
Reserved (must contain 20H)
201A
CCB1
2019
Reserved (must contain 20H)
2018
CCB0
2017
2014
2014
Reserved (each byte must contain FFH)
2013
2000
Lower interrupt vectors