Intel 8XC196MC Benutzerhandbuch
4-5
MEMORY PARTITIONS
4.1.5.1
Memory-mapped SFRs
Locations 1FE0–1FFFH contain memory-mapped SFRs (see Table 4-3). Locations in this range
that are omitted from the table are reserved. The memory-mapped SFRs must be accessed with
indirect or indexed addressing modes, and they cannot be windowed. If you read a location in this
range through a window, the SFR appears to contain FFH (all ones). If you write a location in
this range through a window, the write operation has no effect on the SFR.
that are omitted from the table are reserved. The memory-mapped SFRs must be accessed with
indirect or indexed addressing modes, and they cannot be windowed. If you read a location in this
range through a window, the SFR appears to contain FFH (all ones). If you write a location in
this range through a window, the write operation has no effect on the SFR.
The memory-mapped SFRs are accessed through the memory controller, so instructions that op-
erate on these SFRs execute as they would from external memory with zero wait states.
erate on these SFRs execute as they would from external memory with zero wait states.
4.1.5.2
Peripheral SFRs
Locations 1F00–1FDFH provide access to the peripheral SFRs. Table 4-6 on page 4-8, Table 4-6
on page 4-8, and Table 4-6 on page 4-8 list the peripheral SFRs of the 8XC196MC, 8XC196MD,
and 8XC196MH, respectively. Locations that are omitted from the tables are reserved. The pe-
ripheral SFRs are I/O control registers; they are physically located in the on-chip peripherals.
These peripheral SFRs can be windowed and they can be addressed either as words or bytes, ex-
cept as noted in the tables.
on page 4-8, and Table 4-6 on page 4-8 list the peripheral SFRs of the 8XC196MC, 8XC196MD,
and 8XC196MH, respectively. Locations that are omitted from the tables are reserved. The pe-
ripheral SFRs are I/O control registers; they are physically located in the on-chip peripherals.
These peripheral SFRs can be windowed and they can be addressed either as words or bytes, ex-
cept as noted in the tables.
The peripheral SFRs are accessed directly, without using the memory controller, so instructions
that operate on these SFRs execute as they would if they were operating on the register file.
that operate on these SFRs execute as they would if they were operating on the register file.
Table 4-3. Memory-mapped SFRs
Ports 3, 4, 5, UPROM SFRs
Hex Address
High (Odd) Byte
Low (Even) Byte
1FFE
P4_PIN
P3_PIN
1FFC
P4_REG
P3_REG
• • •
• • •
• • •
1FF6
P5_PIN
USFR
1FF4
P5_REG
Reserved
1FF2
P5_DIR
Reserved
1FF0
P5_MODE
Reserved