Texas Instruments TMS320C642x DSP Benutzerhandbuch
1
Introduction
1.1
Purpose of the Peripheral
1.2
Features
User's Guide
SPRUEM4A – November 2007
DDR2 Memory Controller
This document describes the DDR2 memory controller in the TMS320C642x Digital Signal Processor
(DSP).
(DSP).
The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM
devices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories
are not supported. The DDR2 memory controller is the major memory location for program and data
storage.
devices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories
are not supported. The DDR2 memory controller is the major memory location for program and data
storage.
The DDR2 memory controller supports the following features:
•
JESD79D-2A standard compliant DDR2 SDRAM
•
256 Mbyte memory space
•
Data bus width of 32 or 16 bits (see the device-specific data manual for the mode(s) that are
supported)
supported)
•
CAS latencies: 2, 3, 4, and 5
•
Internal banks: 1, 2, 4, and 8
•
Burst length: 8
•
Burst type: sequential
•
1 CS signal
•
Page sizes: 256, 512, 1024, and 2048
•
SDRAM autoinitialization
•
Self-refresh mode
•
Prioritized refresh
•
Programmable refresh rate and backlog counter
•
Programmable timing parameters
•
Big-endian and little-endian operating modes
SPRUEM4A – November 2007
DDR2 Memory Controller
7