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1.3

Functional Block Diagram

SCR

DDR2

memory

controller

BUS

External
DDR2 SDRAM

DSP

Master

peripherals

EDMA

VPSS

1.4

Supported Use Case Statement

1.5

Industry Standard(s) Compliance Statement

Introduction

The DDR2 memory controller is the main interface to external DDR2 memory.

Figure 1

displays the

general data paths to on-chip peripherals and external DDR2 SDRAM.

Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controller
through the switched central resource (SCR).

Figure 1. Data Paths to DDR2 Memory Controller

The DDR2 memory controller supports JESD79D-2A DDR2-400 SDRAM memories utilizing either 32-bit
or 16-bit of the DDR2 memory controller data bus. See

Section 3

for more details.

The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with the
exception of the following feature list:

•

On Die Termination (ODT). The DDR2 memory controller does not include any on-die terminating
resistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled
by tying the ODT input pin of the DDR2 SDRAM to ground.

•

Differential DQS. The DDR2 memory controller supports single ended DQS signals.

DDR2 Memory Controller

SPRUEM4A – November 2007

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