Texas Instruments SM320F2812-HT Benutzerhandbuch
M51
M50
M47
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M44
M48
M49
M43
LSB
MSB
M52
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
(1)
MASTER
SLAVE
NO.
UNIT
MIN
MAX
MIN
MAX
M49
t
su(DRV-CKXH)
Setup time, DR valid before CLKX high
P – 10
8P – 10
ns
M50
t
h(CKXH-DRV)
Hold time, DR valid after CLKX high
P – 10
8P – 10
ns
M51
t
su(FXL-CKXL)
Setup time, FSX low before CLKX low
8P + 10
ns
M52
t
c(CKX)
Cycle time, CLKX
2P
16P
ns
(1)
Not production tested.
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
(1) (2)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
M43
t
h(CKXH-FXL)
Hold time, FSX low after CLKX high
2P
ns
M44
t
d(FXL-CKXL)
Delay time, FSX low to CLKX low
P
ns
Disable time, DX high impedance following last data bit from FSX
M47
t
dis(FXH-DXHZ)
6
6P + 6
ns
high
M48
t
d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
Not production tested.
(2)
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.
For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV
= 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Electrical Specifications
147
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