Intel 80C196NU Benutzerhandbuch
10-17
EVENT PROCESSOR ARRAY (EPA)
T2CONTROL
Address:
Reset State:
1F94H
00H
The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count
rate for timer 2.
rate for timer 2.
7
0
CE
UD
M2
M1
M0
P2
P1
P0
Bit
Number
Bit
Mnemonic
Function
7
CE
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
disabled and not free running.
0 = disables timer
1 = enables timer
1 = enables timer
6
UD
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
mode bits, M2:0).
0 = count down
1 = count up
1 = count up
5:3
M2:0
EPA Clock Direction Mode Bits.
These bits determine the timer clocking source and direction source
M2 M1
M0 Clock
Source
Direction
Source
0
0
0
f/4
UD bit (T2CONTROL.6)
X
0
1
T2CLK pin
†
UD bit (T2CONTROL.6)
0
1
0
f/4
T2DIR
pin
0
1
1
T2CLK pin
†
T2DIR pin
1
0
0
timer 1 overflow
UD bit (T2CONTROL.6)
1
1
0
timer 1
same as timer 1
1
1
1
quadrature clocking using T2CLK and T2DIR
†
If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
2:0
P2:0
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2
P1
P0
Prescaler
Resolution
†
0
0
0
divide by 1 (disabled)
160 ns
0
0
1
divide by 2
320 ns
0
1
0
divide by 4
640 ns
0
1
1
divide by 8
1.28 µs
1
0
0
divide by 16
2.56 µs
1
0
1
divide by 32
5.12 µs
1
1
0
divide by 64
10.24 µs
1
1
1
divide by 128 (NU only)
20.48 µs
†
At f = 25 MHz. Use the formula on page 10-6 to calculate the
resolution at other frequencies.
Figure 10-9. Timer 2 Control (T2CONTROL) Register