Datenbogen (MC56F8367EVME)InhaltsverzeichnisPart 1 Overview51.1 56F8367/56F8167 Features51.1.1 Core51.1.2 Differences Between Devices51.1.3 Memory61.1.4 Peripheral Circuits61.1.5 Energy Information71.2 Device Description71.2.1 56F8367 Features81.2.2 56F8167 Features81.3 Award-Winning Development Environment91.4 Architecture Block Diagram101.5 Product Documentation141.6 Data Sheet Conventions14Part 2 Signal/Connection Descriptions152.1 Introduction152.2 Signal Pins18Part 3 On-Chip Clock Synthesis (OCCS)393.1 Introduction393.2 External Clock Operation393.2.1 Crystal Oscillator393.2.2 Ceramic Resonator (Default)403.2.3 External Clock Source403.3 Registers41Part 4 Memory Operating Modes (MEM)414.1 Introduction414.2 Program Map424.3 Interrupt Vector Table434.4 Data Map474.5 Flash Memory Map474.6 EOnCE Memory Map494.7 Peripheral Memory Mapped Registers494.8 Factory Programmed Memory80Part 5 Interrupt Controller (ITCN)815.1 Introduction815.2 Features815.3 Functional Description815.3.1 Normal Interrupt Handling815.3.2 Interrupt Nesting815.3.3 Fast Interrupt Handling825.4 Block Diagram835.5 Operating Modes835.6 Register Descriptions845.6.1 Interrupt Priority Register 0 (IPR0)865.6.1.1 Reserved-Bits 15-14865.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)- Bits13-12865.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)- Bits 11-10865.6.1.4 Reserved-Bits 9-0865.6.2 Interrupt Priority Register 1 (IPR1)865.6.2.1 Reserved-Bits 15-6875.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)-Bits 5-4875.6.2.3 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)-Bits 3-2875.6.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)-Bits 1-0875.6.3 Interrupt Priority Register 2 (IPR2)875.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)-Bits 15-14885.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)- Bits 13-12885.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)-Bits 11-10885.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)-Bits 9-8885.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)-Bits 7-6895.6.3.6 Reserved-Bits 5-4895.6.3.7 External IRQ B Interrupt Priority Level (IRQB IPL)-Bits 3-2895.6.3.8 External IRQ A Interrupt Priority Level (IRQA IPL)-Bits 1-0895.6.4 Interrupt Priority Register 3 (IPR3)895.6.4.1 GPIOD Interrupt Priority Level (GPIOD IPL)-Bits 15-14895.6.4.2 GPIOE Interrupt Priority Level (GPIOE IPL)-Bits 13-12905.6.4.3 GPIOF Interrupt Priority Level (GPIOF IPL)-Bits 11-10905.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)- Bits 9-8905.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)-Bits 7-6905.6.4.6 FlexCAN Error Interrupt Priority Level (FCERR IPL)- Bits 5-4905.6.4.7 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)- Bits 3-2915.6.4.8 Reserved-Bits 1-0915.6.5 Interrupt Priority Register 4 (IPR4)915.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)-Bits 15-14915.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)- Bits 13-12915.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)-Bits 11-10925.6.5.4 Reserved-Bits 9-6925.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)-Bits 5-4925.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)-Bits 3-2925.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)-Bits 1-0925.6.6 Interrupt Priority Register 5 (IPR5)935.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)-Bits 15-14935.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)-Bits 13-12935.6.6.3 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)-Bits 11-10935.6.6.4 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)-Bits 9-8935.6.6.5 Reserved-Bits 7-6945.6.6.6 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)-Bits 5-4945.6.6.7 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)- Bits 3-2945.6.6.8 SPI0 Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)- Bits 1-0945.6.7 Interrupt Priority Register 6 (IPR6)945.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)-Bits 15-14955.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)-Bits 13-12955.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)-Bits 11-10955.6.7.4 Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)-Bits 9-8955.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)-Bits 7-6955.6.7.6 Reserved-Bits 5-4965.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)-Bits 3-2965.6.7.8 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)-Bits 1-0965.6.8 Interrupt Priority Register 7 (IPR7)965.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)-Bits 15-14965.6.8.2 Timer B, Channel 3 Interrupt Priority Level (TMRB3 IPL)-Bits 13-12975.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)-Bits 11-10975.6.8.4 Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)-Bits 9-8975.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)-Bits 7-6975.6.8.6 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)-Bits 5-4975.6.8.7 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)-Bits 3-2985.6.8.8 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)-Bits 1-0985.6.9 Interrupt Priority Register 8 (IPR8)985.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)-Bits 15-14985.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)- Bits 13-12985.6.9.3 Reserved-Bits 11-10995.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)-Bits 9-8995.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)- Bits 7-6995.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)-Bits 5-4995.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)-Bits 3-2995.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)-Bits 1-01005.6.10 Interrupt Priority Register 9 (IPR9)1005.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)-Bits 15-141005.6.10.2 PWM B Fault Interrupt Priority Level (PWMB_F IPL)-Bits 13-121005.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)-Bits 11-101005.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)-Bits 9-81015.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)-Bits 7-61015.6.10.6 ADC B Zero Crossing or Limit Error Interrupt Priority Level (ADCB_ZC IPL)-Bits 5-41015.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)-Bits 3-21015.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)-Bits 1-01025.6.11 Vector Base Address Register (VBA)1025.6.11.1 Reserved-Bits 15-131025.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)- Bits 12-01025.6.12 Fast Interrupt 0 Match Register (FIM0)1025.6.12.1 Reserved-Bits 15-71025.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)-Bits 6-01025.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)1035.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)-Bits 15-01035.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)1035.6.14.1 Reserved-Bits 15-51035.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)-Bits 4-01035.6.15 Fast Interrupt 1 Match Register (FIM1)1035.6.15.1 Reserved-Bits 15-71035.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)-Bits 6-01045.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)1045.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)-Bits 15-01045.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)1045.6.17.1 Reserved-Bits 15-51045.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)-Bits 4-01045.6.18 IRQ Pending 0 Register (IRQP0)1045.6.18.1 IRQ Pending (PENDING)-Bits 16-21055.6.18.2 Reserved-Bit 01055.6.19 IRQ Pending 1 Register (IRQP1)1055.6.19.1 IRQ Pending (PENDING)-Bits 32-171055.6.20 IRQ Pending 2 Register (IRQP2)1055.6.20.1 IRQ Pending (PENDING)-Bits 48-331055.6.21 IRQ Pending 3 Register (IRQP3)1065.6.21.1 IRQ Pending (PENDING)-Bits 64-491065.6.22 IRQ Pending 4 Register (IRQP4)1065.6.22.1 IRQ Pending (PENDING)-Bits 80-651065.6.23 IRQ Pending 5 Register (IRQP5)1065.6.23.1 Reserved-Bits 96-861065.6.23.2 IRQ Pending (PENDING)-Bits 81-851075.6.24 Reserved-Base + 171075.6.25 Reserved-Base + 181075.6.26 Reserved-Base + 191075.6.27 Reserved-Base + 1A1075.6.28 Reserved-Base + 1B1075.6.29 Reserved-Base + 1C1075.6.30 ITCN Control Register (ICTL)1075.6.30.1 Interrupt (INT)-Bit 151075.6.30.2 Interrupt Priority Level (IPIC)-Bits 14-131075.6.30.3 Vector Number - Vector Address Bus (VAB)-Bits 12-61085.6.30.4 Interrupt Disable (INT_DIS)-Bit 51085.6.30.5 Reserved-Bit 41085.6.30.6 IRQB State Pin (IRQB STATE)-Bit 31085.6.30.7 IRQA State Pin (IRQA STATE)-Bit 21085.6.30.8 IRQB Edge Pin (IRQB Edg)-Bit 11085.6.30.9 IRQA Edge Pin (IRQA Edg)-Bit 01085.6.31 Reserved-Base + $1E1085.6.32 Interrupt Priority Register 10 (IPR10)1085.6.32.1 Reserved-Bits 15 - 81095.6.32.2 FlexCAN2 Message Buffer Interrupt Priority Level (FlexCAN2_MSGBUF IPL)-Bits 7 - 61095.6.32.3 FlexCAN2 Wake Up Interrupt Priority Level (FlexCAN2_WKUP IPL)- Bits 5 - 41095.6.32.4 FlexCAN2 Error Interrupt Priority Level (FlexCAN2_ERR IPL)-Bits 3 - 21095.6.32.5 FlexCAN2 Bus-Off Interrupt Priority Level (FlexCAN2_BOFF IPL)- Bits 1 - 01095.7 Resets1105.7.1 Reset Handshake Timing1105.7.2 ITCN After Reset110Part 6 System Integration Module (SIM)1116.1 Overview1116.2 Features1116.3 Operating Modes1126.4 Operating Mode Register1126.5 Register Descriptions1136.5.1 SIM Control Register (SIM_CONTROL)1146.5.1.1 Reserved-Bits 15-71146.5.1.2 EMI_MODE (EMI_MODE)-Bit 61156.5.1.3 OnCE Enable (OnCE EBL)-Bit 51156.5.1.4 Software Reset (SW RST)-Bit 41156.5.1.5 Stop Disable (STOP_DISABLE)-Bits 3-21156.5.1.6 Wait Disable (WAIT_DISABLE)-Bits 1-01156.5.2 SIM Reset Status Register (SIM_RSTSTS)1156.5.2.1 Reserved-Bits 15-61166.5.2.2 Software Reset (SWR)-Bit 51166.5.2.3 COP Reset (COPR)-Bit 41166.5.2.4 External Reset (EXTR)-Bit 31166.5.2.5 Power-On Reset (POR)-Bit 21166.5.2.6 Reserved-Bits 1-01166.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)1166.5.3.1 Software Control Data 1 (FIELD)-Bits 15-01166.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)1176.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)1176.5.6 SIM Pull-up Disable Register (SIM_PUDR)1176.5.6.1 Reserved -Bit 151176.5.6.2 PWMA1-Bit 141176.5.6.3 CAN-Bit 131186.5.6.4 EMI_MODE-Bit 121186.5.6.5 RESET-Bit 111186.5.6.6 IRQ-Bit 101186.5.6.7 XBOOT-Bit 91186.5.6.8 PWMB-Bit 81186.5.6.9 PWMA0-Bit 71186.5.6.10 Reserved-Bit 61186.5.6.11 CTRL-Bit 51186.5.6.12 Reserved-Bit 41186.5.6.13 JTAG-Bit 31186.5.6.14 Reserved-Bit 2-01186.5.7 CLKO Select Register (SIM_CLKOSR)1186.5.7.1 Reserved-Bits 15-101196.5.7.2 Alternate GPIOB Peripheral Function for A23 (A23)-Bit 91196.5.7.3 Alternate GPIOB Peripheral Function for A22 (A22)-Bit 81196.5.7.4 Alternate GPIOB Peripheral Function for A21 (A21)-Bit 71196.5.7.5 Alternate GPIOB Peripheral Function fpr A20 (A20)-Bit 61196.5.7.6 Clockout Disable (CLKDIS)-Bit 51196.5.7.7 CLockout Select (CLKOSEL)-Bits 4-01196.5.8 GPIO Peripheral Select Register (SIM_GPS)1206.5.8.1 Reserved-Bits 15-61226.5.8.2 GPIOD1 (D1)-Bit 51236.5.8.3 GPIOD0 (D0)-Bit 41236.5.8.4 GPIOC3 (C3)-Bit 31236.5.8.5 GPIOC2 (C2)-Bit 21236.5.8.6 GPIOC1 (C1)-Bit 11236.5.8.7 GPIOC0 (C0)-Bit 01236.5.9 Peripheral Clock Enable Register (SIM_PCE)1236.5.9.1 External Memory Interface Enable (EMI)-Bit 151246.5.9.2 Analog-to-Digital Converter B Enable (ADCB)-Bit 141246.5.9.3 Analog-to-Digital Converter A Enable (ADCA)-Bit 131246.5.9.4 FlexCAN Enable (CAN)-Bit 121246.5.9.5 Decoder 1 Enable (DEC1)-Bit 111246.5.9.6 Decoder 0 Enable (DEC0)-Bit 101246.5.9.7 Quad Timer D Enable (TMRD)-Bit 91246.5.9.8 Quad Timer C Enable (TMRC)-Bit 81246.5.9.9 Quad Timer B Enable (TMRB)-Bit 71256.5.9.10 Quad Timer A Enable (TMRA)-Bit 61256.5.9.11 Serial Communications Interface 1 Enable (SCI1)-Bit 51256.5.9.12 Serial Communications Interface 0 Enable (SCI0)-Bit 41256.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)-Bit 31256.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)-Bit 21256.5.9.15 Pulse Width Modulator B Enable (PWMB)-11256.5.9.16 Pulse Width Modulator A Enable (PWMA)-01256.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)1266.5.10.1 Input/Output Short Address Low (ISAL[23:22])-Bit 1-01266.5.10.2 Input/Output Short Address Low (ISAL[21:6])-Bit 15-01276.5.11 Peripheral Clock Enable Register 2 (SIM_PCE2)1276.5.11.1 Reserved-Bits 15-11276.5.11.2 CAN2 Enable-Bit 01276.6 Clock Generation Overview1276.7 Power Down Modes Overview1286.8 Stop and Wait Mode Disable Function1286.9 Resets129Part 7 Security Features1297.1 Operation with Security Enabled1297.2 Flash Access Blocking Mechanisms1307.2.1 Forced Operating Mode Selection1307.2.2 Disabling EOnCE Access1307.2.3 Flash Lockout Recovery1307.2.4 Product Analysis132Part 8 General Purpose Input/Output (GPIO)1328.1 Introduction1328.2 Memory Maps1328.3 Configuration133Part 9 Joint Test Action Group (JTAG)1379.1 56F8367 Information137Part 10 Specifications13810.1 General Characteristics13810.2 DC Electrical Characteristics14210.2.1 Temperature Sense14510.3 AC Electrical Characteristics14610.4 Flash Memory Characteristics14710.5 External Clock Operation Timing14710.6 Phase Locked Loop Timing14810.7 Crystal Oscillator Timing14810.8 External Memory Interface Timing14910.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing15110.10 Serial Peripheral Interface (SPI) Timing15410.11 Quad Timer Timing15710.12 Quadrature Decoder Timing15710.13 Serial Communication Interface (SCI) Timing15810.14 Controller Area Network (CAN) Timing15910.15 JTAG Timing15910.16 Analog-to-Digital Converter (ADC) Parameters16110.17 Equivalent Circuit for ADC Inputs16410.18 Power Consumption164Part 11 Packaging16611.1 56F8367 Package and Pin-Out Information16611.2 56F8167 Package and Pin-Out Information173Part 12 Design Considerations17712.1 Thermal Design Considerations17712.2 Electrical Design Considerations17812.3 Power Distribution and I/O Ring Implementation179Part 13 Ordering Information180Größe: 973 KBSeiten: 182Language: EnglishHandbuch öffnen
Benutzerhandbuch (MC56F8367EVME)InhaltsverzeichnisPreface9Chapter 1 Introduction131.1 56F8367EVM Architecture141.2 56F8367EVM Configuration Jumpers151.3 56F8367EVM Connections17Chapter 2 Technical Summary192.1 MC56F8367222.2 Program and Data Memory222.2.1 SRAM Bank 0232.2.2 SRAM Bank 1242.3 RS-232 Serial Communications252.4 Clock Source262.5 Operating Mode272.5.1 EXTBOOT272.5.2 EMI_MODE272.5.3 CLKMODE282.6 Debug LEDs282.7 Debug Support292.7.1 JTAG Connector302.7.2 Parallel JTAG Interface Connector312.8 External Interrupts332.9 Reset342.10 Power Supply352.11 Daughter Card Connectors362.11.1 Peripheral Daughter Card Connector362.11.2 Memory Daughter Card Connector382.12 Motor Control PWM Signals and LEDs402.13 CAN Interfaces412.13.1 FlexCAN #1 Interface412.13.2 FlexCAN #2 Interface422.14 Software Feature Jumpers442.15 Peripheral Expansion Connectors452.15.1 Address Bus Expansion Connector462.15.2 Data Bus Expansion Connector472.15.3 External Memory Control Signal Expansion Connector482.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector482.15.5 Encoder #1 / SPI #1 Expansion Connector492.15.6 Timer Channel C Expansion Connector492.15.7 Timer Channel D Expansion Connector502.15.8 A/D Port A Expansion Connector512.15.9 A/D Port B Expansion Connector522.15.10 Serial Communications Port #0 Expansion Connector522.15.11 Serial Communications Port #1 Expansion Connector532.15.12 Serial Peripheral Interface #0 Expansion Connector532.15.13 FlexCAN #1 Expansion Connector542.15.14 FlexCAN #2 Expansion Connector542.15.15 PWM Port A Expansion Connector552.15.16 PWM Port B Expansion Connector552.16 Test Points56Appendix A 56F8367EVM Schematics57Appendix B 56F8367EVM Bill of Material73Größe: 1,33 MBSeiten: 80Language: EnglishHandbuch öffnen
