Benutzerhandbuch für Freescale Semiconductor Lite5200B: Evaluation Board for the MPC5200B CWMPCEVB5200BE

Inhaltsverzeichnis

• 1 Electrical and Thermal Characteristics

  4
  • 1.1 DC Electrical Characteristics

    4
    • 1.1.1 Absolute Maximum Ratings

      4
    • 1.1.2 Recommended Operating Conditions

      4
    • 1.1.3 DC Electrical Specifications

      5
    • 1.1.4 Electrostatic Discharge

      7
    • 1.1.5 Power Dissipation

      7
    • 1.1.6 Thermal Characteristics

      9
      • 1.1.6.1 Heat Dissipation

        9
  • 1.2 Oscillator and PLL Electrical Characteristics

    10
    • 1.2.1 System Oscillator Electrical Characteristics

      11
    • 1.2.2 RTC Oscillator Electrical Characteristics

      11
    • 1.2.3 System PLL Electrical Characteristics

      11
    • 1.2.4 e300 Core PLL Electrical Characteristics

      11
  • 1.3 AC Electrical Characteristics

    12
    • 1.3.1 AC Test Timing Conditions:

      12
    • 1.3.2 AC Operating Frequency Data

      13
    • 1.3.3 Clock AC Specifications

      13
    • 1.3.4 Resets

      14
      • 1.3.4.1 Reset Configuration Word

        15
    • 1.3.5 External Interrupts

      15
    • 1.3.6 SDRAM

      17
      • 1.3.6.1 Memory Interface Timing-Standard SDRAM Read Command

        17
      • 1.3.6.2 Memory Interface Timing-Standard SDRAM Write Command

        18
      • 1.3.6.3 Memory Interface Timing-DDR SDRAM Read Command

        19
      • 1.3.6.4 Memory Interface Timing-DDR SDRAM Write Command

        21
    • 1.3.7 PCI

      21
    • 1.3.8 Local Plus Bus

      23
      • 1.3.8.1 Non-MUXed Mode

        23
      • 1.3.8.2 Burst Mode

        25
      • 1.3.8.3 MUXed Mode

        27
    • 1.3.9 ATA

      28
    • 1.3.10 Ethernet

      38
    • 1.3.11 USB

      40
    • 1.3.12 SPI

      41
    • 1.3.13 MSCAN

      45
    • 1.3.14 I2C

      45
    • 1.3.15 J1850

      46
    • 1.3.16 PSC

      47
      • 1.3.16.1 Codec Mode (8-,16-, 24-, and 32-bit)/I2S Mode

        47
      • 1.3.16.2 AC97 Mode

        49
      • 1.3.16.3 IrDA Mode

        49
      • 1.3.16.4 SPI Mode

        50
    • 1.3.17 GPIOs and Timers

      54
      • 1.3.17.1 General and Asynchronous Signals

        54
    • 1.3.18 IEEE 1149.1 (JTAG) AC Specifications

      56
• 2 Package Description

  57
  • 2.1 Package Parameters

    57
  • 2.2 Mechanical Dimensions

    58
  • 2.3 Pinout Listings

    59
• 3 System Design Information

  64
  • 3.1 Power Up/Down Sequencing

    64
    • 3.1.1 Power Up Sequence

      65
    • 3.1.2 Power Down Sequence

      65
  • 3.2 System and CPU Core AVDD Power Supply Filtering

    65
  • 3.3 Pull-up/Pull-down Resistor Requirements

    65
    • 3.3.1 Pull-down Resistor Requirements for TEST pins

      65
    • 3.3.2 Pull-up Requirements for the PCI Control Lines

      66
    • 3.3.3 Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)

      66
    • 3.3.4 .Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit Mode)

      66
  • 3.4 JTAG

    66
    • 3.4.1 JTAG_TRST

      66
      • 3.4.1.1 JTAG_TRST and PORRESET

        66
      • 3.4.1.2 Connecting JTAG_TRST

        66
    • 3.4.2 e300 COP / BDM Interface

      67
      • 3.4.2.1 Boards Interfacing the JTAG Port via a COP Connector

        67
      • 3.4.2.2 Boards Without COP Connector

        68
• 4 Ordering Information

  69
• 5 Document Revision History

  70