Ficha De Dados (CWMPCEVB5200BE)índice analítico1 Electrical and Thermal Characteristics41.1 DC Electrical Characteristics41.1.1 Absolute Maximum Ratings41.1.2 Recommended Operating Conditions41.1.3 DC Electrical Specifications51.1.4 Electrostatic Discharge71.1.5 Power Dissipation71.1.6 Thermal Characteristics91.1.6.1 Heat Dissipation91.2 Oscillator and PLL Electrical Characteristics101.2.1 System Oscillator Electrical Characteristics111.2.2 RTC Oscillator Electrical Characteristics111.2.3 System PLL Electrical Characteristics111.2.4 e300 Core PLL Electrical Characteristics111.3 AC Electrical Characteristics121.3.1 AC Test Timing Conditions:121.3.2 AC Operating Frequency Data131.3.3 Clock AC Specifications131.3.4 Resets141.3.4.1 Reset Configuration Word151.3.5 External Interrupts151.3.6 SDRAM171.3.6.1 Memory Interface Timing-Standard SDRAM Read Command171.3.6.2 Memory Interface Timing-Standard SDRAM Write Command181.3.6.3 Memory Interface Timing-DDR SDRAM Read Command191.3.6.4 Memory Interface Timing-DDR SDRAM Write Command211.3.7 PCI211.3.8 Local Plus Bus231.3.8.1 Non-MUXed Mode231.3.8.2 Burst Mode251.3.8.3 MUXed Mode271.3.9 ATA281.3.10 Ethernet381.3.11 USB401.3.12 SPI411.3.13 MSCAN451.3.14 I2C451.3.15 J1850461.3.16 PSC471.3.16.1 Codec Mode (8-,16-, 24-, and 32-bit)/I2S Mode471.3.16.2 AC97 Mode491.3.16.3 IrDA Mode491.3.16.4 SPI Mode501.3.17 GPIOs and Timers541.3.17.1 General and Asynchronous Signals541.3.18 IEEE 1149.1 (JTAG) AC Specifications562 Package Description572.1 Package Parameters572.2 Mechanical Dimensions582.3 Pinout Listings593 System Design Information643.1 Power Up/Down Sequencing643.1.1 Power Up Sequence653.1.2 Power Down Sequence653.2 System and CPU Core AVDD Power Supply Filtering653.3 Pull-up/Pull-down Resistor Requirements653.3.1 Pull-down Resistor Requirements for TEST pins653.3.2 Pull-up Requirements for the PCI Control Lines663.3.3 Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)663.3.4 .Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit Mode)663.4 JTAG663.4.1 JTAG_TRST663.4.1.1 JTAG_TRST and PORRESET663.4.1.2 Connecting JTAG_TRST663.4.2 e300 COP / BDM Interface673.4.2.1 Boards Interfacing the JTAG Port via a COP Connector673.4.2.2 Boards Without COP Connector684 Ordering Information695 Document Revision History70Tamanho: 1000 KBPáginas: 72Language: EnglishAbrir o manual