Benutzerhandbuch für Inova ICP-PII

Inhaltsverzeichnis

• Contents

  3
  • Unpacking and Special Handling Instructions

    8
  • Revision History

    9
  • Three Year Limited Warranty

    10
  • 1.0 ICP-PIII CPU

    12
  • 1.01 Interfacing

    13
  • 1.02 Peripherals

    13
  • 1.03 Software

    13
  • 1.04 Graphics

    13
  • 1.1 Specifications

    14
  • 1.2 Configuration

    16
  • Table 1.20 ‘Processor Overview

    16
  • Figure 1.20 ICP-PIII Overview

    17
  • 1.3 Software

    18
  • 1.31 Linux

    18
  • 1.32 VentureCom

    18
  • 1.33 Windows 2000

    18
  • 1.34 Windows CE

    19
  • 1.35 VxWorks

    19
  • 1.36 OS-9 x86

    19
  • 1.37 QNX

    19
  • 1.38 Jbed

    19
  • 1.4 Hardware

    20
  • 1.41 Block Diagram

    20
  • Figure 1.41 Block Diagram

    20
  • 1.42 Connector Location

    21
  • Figure 1.42 Connector Locations

    21
  • 1.43 Connector Description

    21
  • Table 1.43 Connector Description

    21
  • Table 1.43 Continued

    22
  • 1.44 Front-Panel Features

    22
  • Table 1.44 Front Panels

    22
  • Figure 1.44 Front-Panel Options

    23
  • 1.45 Interface Positions

    24
  • Figure 1.45 Interfaces

    24
  • 2.0 Memory Map

    26
  • Figure 2.00 System Architecture

    26
  • Table 2.00 UMB Reservations for ISA

    27
  • Table 2.01 Port Addressing

    27
  • 2.1 I/O Mapped Peripherals

    28
  • Table 2.10 Legacy I/O Map (ISA Compatible)

    28
  • 2.2 Memory Mapped Peripherals

    29
  • 2.3 Interrupt Routing

    29
  • Table 2.30 PC-AT Interrupt Definitions

    30
  • 2.4 Inova PIII Device List

    31
  • Table 2.40 Legacy I/O Map (ISA Compatible)

    31
  • 2.5 Interrupt Configuration

    32
  • Table 2.50 CompactPCI Bus Interrupts

    32
  • 2.6 Timer / Counter

    33
  • 2.7 Watchdog

    33
  • 3.0 CompactPCI J1/J2 Connector

    37
  • 3.01 CompactPCI Connector

    37
  • Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector

    37
  • 3.02 ICP-PIII Connector J1 and J2

    37
  • Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment

    38
  • Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)

    39
  • Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)

    40
  • Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)

    41
  • Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)

    42
  • Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration

    43
  • 3.1 CompactPCI Backplane

    44
  • Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot

    45
  • 3.2 Interfaces

    46
  • 3.21 J7 & J12 Fast Ethernet

    46
  • Figure 3.21 RJ45 Pinout

    46
  • Table 3.21 Ethernet Connector Signals

    46
  • 3.22 J17 VGA Interface

    47
  • Figure 3.22 High-Density D-Sub VGA Interface Pinout

    47
  • Table 3.22 Video Output Connector Signals

    47
  • Table 3.22b Video Resolutions

    48
  • 3.23 J16 PanelLink Interface

    49
  • Figure 3.23 PanelLink Interface Connector

    49
  • Table 2.12 PanelLink Interface

    49
  • 2.24 J16 GigaSTAR Interface

    50
  • Figure 2.24 GigaSTAR D-Sub Interface Pinout

    50
  • Table 2.11 GigaSTAR Interface

    50
  • 3.25 J19 USB Interface

    51
  • Figure 3.25 USB Interface Pinout

    51
  • Table 3.25 USB Connector Signals

    51
  • 3.26 J15 FireWire Interface

    52
  • Figure 3.26 FireWire Interface Pinout

    52
  • Table 3.26 FireWire Connector Signals

    52
  • 3.27 J20 Infrared (iRdA) Interface

    53
  • 3.28 J20 Reset Button

    53
  • 3.29 J14 FLASH Interface

    53
  • 3.30 J18 Floppy Disk Interface

    53
  • 3.31 Connecting the PIII to the Inova IPB-FPE8

    54
  • Figure 3.31 CPU to IPB-FPE8 Connection

    54
  • 3.32 Connecting the PIII to the Inova ICP-HD-1

    55
  • Figure 3.32 CPU to ICP-HD-1 Connection

    55
  • 3.33 Connecting the PIII to the Inova IPB-FPE12

    56
  • Figure 3.33 CPU to IPB-FPE12 Connection

    56
  • 3.34 Connecting the PIII to the Inova IPB-FPE12

    57
  • Figure 3.34 CPU to IPB-FPE12 Connection

    57
  • 3.35 Connecting the PIII to the ICP-FD-1

    58
  • Figure 3.35 CPU to Slim-Line Floppy Disk Connection

    58
  • A1 IPB-FPE8 CPU Extension

    60
  • A1.1 J11 Interface for COM1, Mouse & Keyboard

    60
  • A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)

    60
  • Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU

    60
  • A1.3 Stand-Alone IPB-FPE8

    61
  • Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8

    61
  • A1.4 IPB-FPE8MS (Theme Variation)

    62
  • Figure A1.4 Piggyback Interface IPB-FPE8MS

    62
  • Table A1.4 IPB-FPE8MS Connector Description

    62
  • A1.5 IPB-FPE8MS Description

    63
  • Figure A1.5 Top & Bottom Views of the IPB-FPE8MS

    63
  • Table A1.5 Standard Hard-Disk & Floppy Disk Connectors

    63
  • A1.6 Keyboard Interface

    64
  • Figure A1.6 Keyboard Interface Pinout

    64
  • Table A1.6 Keyboard Connector Signals

    64
  • A1.7 Mouse Interface

    64
  • Figure A1.7 Mouse Interface Pinout

    64
  • Table A1.7 Mouse Connector Signals

    64
  • A1.8 COM1 Interface

    65
  • Figure A1.8 COM1 Interface Pinout

    65
  • Table A1.8 COM1 Connector Signals

    65
  • B1 ICP-HD CPU Extension

    68
  • B1.1 J11, J13 Interfaces

    68
  • B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)

    68
  • Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU

    68
  • B1.3 IDE Carrier Board ICP-HD-1

    69
  • Figure B1.3 IDE Carrier Board ICP-HD1

    69
  • Table B1.3 ICP-HD-1 Connector Description

    70
  • B1.4 ICP-HDE8MS (Theme Variation)

    70
  • Figure B1.4 IDE Carrier ICP-HDE8MS

    70
  • Table B1.4 IPB-HDE8MS Connector Description

    71
  • B1.5 ICP-HDE8MS Description

    72
  • Figure B1.5 Top & Bottom Views of the ICP-HDE8MS

    72
  • B1.6 Keyboard Interface

    73
  • Figure B1.6 Keyboard Interface Pinout

    73
  • Table B1.6 Keyboard Connector Signals

    73
  • B1.7 Mouse Interface

    73
  • Figure B1.7 Mouse Interface Pinout

    73
  • Table B1.7 Mouse Connector Signals

    73
  • B1.8 COM1 & COM 2 Interfaces

    74
  • Figure B1.8 COM1 & COM2 Interface Pinout

    74
  • Table B1.8 COM1 & COM2 Connector Signals

    74
  • B1 IPM-ATA CPU Extension

    76
  • B1.1 J1 Interfaces

    76
  • Figure B1.1a Dedicated IPM-ATA Backplane

    76
  • B1.1 J1 Interfaces (Contd.)

    77
  • Figure B1.1b The Complete Connection Picture

    77
  • B1.2 IPM-ATA-HD

    78
  • Figure B1.2 IPM-ATA-HD Board Layout

    78
  • Table B1.2 IPM-ATA-HD Jumper Description

    78
  • B1.3 IPM-ATA-CF

    79
  • Figure B1.3 IPM-ATA-CF Board Layout

    79
  • Table B1.3 IPM-ATA-CF Jumper Description

    79
  • B1.4 IPM-ATA-PCMCIA

    80
  • Figure B1.4 IPM-ATA-PCMCIA Board Layout

    80
  • Table B1.4 IPM-ATA-PCMCIA Jumper Description

    80
  • B1.5 Device Compatibility

    81
  • Table B1.5 Compatibility List

    81
  • C1 IPB-FPE12 CPU Extension

    84
  • C1.1 J13 Interface for LPT1 & COM2

    84
  • C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)

    84
  • Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU

    84
  • C1.3 LPT1 & COM2 Piggyback

    85
  • Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12

    85
  • Table C1.3 IPB-FPE12 Connector Description

    86
  • C1.4 LPT1 Interface

    87
  • Figure C1.6 LPT1 Interface Pinout

    87
  • Table C1.6 LPT1 Connector Signals

    87
  • C1.5 COM2 Interface

    88
  • Figure C1.5 COM2 Interface Pinout

    88
  • Table C1.5 COM2 Connector Signals

    88
  • D1 IPB-RIO CPU Extension

    90
  • D1.1 IPB-RIO-HD-FD

    90
  • Figure D1.1 IPB-RIO-HD-FD

    90
  • D1.2 IPB-RIO-HD-LPT-(FLEX)

    91
  • Figure D1.2 IPB-RIO-HD-LPT-(FLEX)

    91
  • D1.3 IPB-RIO-C-SHORT

    92
  • Figure D1.3 IPB-RIO-C-SHORT

    92
  • Table D1.3 Rear I/O Type ‘C’

    92
  • D1.4 IPB-RIO-C-80MM

    93
  • Figure D1.4 IPB-RIO-C-80MM

    93
• Overview Contents

  11
  • 1.0 ICP-PIII CPU

    12
  • 1.01 Interfacing

    13
  • 1.02 Peripherals

    13
  • 1.03 Software

    13
  • 1.04 Graphics

    13
  • 1.1 Specifications

    14
  • 1.2 Configuration

    16
  • Table 1.20 ‘Processor Overview

    16
  • Figure 1.20 ICP-PIII Overview

    17
  • 1.3 Software

    18
  • 1.31 Linux

    18
  • 1.32 VentureCom

    18
  • 1.33 Windows 2000

    18
  • 1.34 Windows CE

    19
  • 1.35 VxWorks

    19
  • 1.36 OS-9 x86

    19
  • 1.37 QNX

    19
  • 1.38 Jbed

    19
  • 1.4 Hardware

    20
  • 1.41 Block Diagram

    20
  • Figure 1.41 Block Diagram

    20
  • 1.42 Connector Location

    21
  • Figure 1.42 Connector Locations

    21
  • 1.43 Connector Description

    21
  • Table 1.43 Connector Description

    21
  • Table 1.43 Continued

    22
  • 1.44 Front-Panel Features

    22
  • Table 1.44 Front Panels

    22
  • Figure 1.44 Front-Panel Options

    23
  • 1.45 Interface Positions

    24
  • Figure 1.45 Interfaces

    24
• Configuration Contents

  25
  • 2.0 Memory Map

    26
  • Figure 2.00 System Architecture

    26
  • Table 2.00 UMB Reservations for ISA

    27
  • Table 2.01 Port Addressing

    27
  • 2.1 I/O Mapped Peripherals

    28
  • Table 2.10 Legacy I/O Map (ISA Compatible)

    28
  • 2.2 Memory Mapped Peripherals

    29
  • 2.3 Interrupt Routing

    29
  • Table 2.30 PC-AT Interrupt Definitions

    30
  • 2.4 Inova PIII Device List

    31
  • Table 2.40 Legacy I/O Map (ISA Compatible)

    31
  • 2.5 Interrupt Configuration

    32
  • Table 2.50 CompactPCI Bus Interrupts

    32
  • 2.6 Timer / Counter

    33
  • 2.7 Watchdog

    33
• Interfaces Contents

  35
  • 3.0 CompactPCI J1/J2 Connector

    37
  • 3.01 CompactPCI Connector

    37
  • Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector

    37
  • 3.02 ICP-PIII Connector J1 and J2

    37
  • Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment

    38
  • Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)

    39
  • Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)

    40
  • Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)

    41
  • Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)

    42
  • Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration

    43
  • 3.1 CompactPCI Backplane

    44
  • Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot

    45
  • 3.2 Interfaces

    46
  • 3.21 J7 & J12 Fast Ethernet

    46
  • Figure 3.21 RJ45 Pinout

    46
  • Table 3.21 Ethernet Connector Signals

    46
  • 3.22 J17 VGA Interface

    47
  • Figure 3.22 High-Density D-Sub VGA Interface Pinout

    47
  • Table 3.22 Video Output Connector Signals

    47
  • Table 3.22b Video Resolutions

    48
  • 3.23 J16 PanelLink Interface

    49
  • Figure 3.23 PanelLink Interface Connector

    49
  • Table 2.12 PanelLink Interface

    49
  • 2.24 J16 GigaSTAR Interface

    50
  • Figure 2.24 GigaSTAR D-Sub Interface Pinout

    50
  • Table 2.11 GigaSTAR Interface

    50
  • 3.25 J19 USB Interface

    51
  • Figure 3.25 USB Interface Pinout

    51
  • Table 3.25 USB Connector Signals

    51
  • 3.26 J15 FireWire Interface

    52
  • Figure 3.26 FireWire Interface Pinout

    52
  • Table 3.26 FireWire Connector Signals

    52
  • 3.27 J20 Infrared (iRdA) Interface

    53
  • 3.28 J20 Reset Button

    53
  • 3.29 J14 FLASH Interface

    53
  • 3.30 J18 Floppy Disk Interface

    53
  • 3.31 Connecting the PIII to the Inova IPB-FPE8

    54
  • Figure 3.31 CPU to IPB-FPE8 Connection

    54
  • 3.32 Connecting the PIII to the Inova ICP-HD-1

    55
  • Figure 3.32 CPU to ICP-HD-1 Connection

    55
  • 3.33 Connecting the PIII to the Inova IPB-FPE12

    56
  • Figure 3.33 CPU to IPB-FPE12 Connection

    56
  • 3.34 Connecting the PIII to the Inova IPB-FPE12

    57
  • Figure 3.34 CPU to IPB-FPE12 Connection

    57
  • 3.35 Connecting the PIII to the ICP-FD-1

    58
  • Figure 3.35 CPU to Slim-Line Floppy Disk Connection

    58
• IPB-FPE8 Contents

  59
  • A1 IPB-FPE8 CPU Extension

    60
  • A1.1 J11 Interface for COM1, Mouse & Keyboard

    60
  • A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)

    60
  • Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU

    60
  • A1.3 Stand-Alone IPB-FPE8

    61
  • Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8

    61
  • A1.4 IPB-FPE8MS (Theme Variation)

    62
  • Figure A1.4 Piggyback Interface IPB-FPE8MS

    62
  • Table A1.4 IPB-FPE8MS Connector Description

    62
  • A1.5 IPB-FPE8MS Description

    63
  • Figure A1.5 Top & Bottom Views of the IPB-FPE8MS

    63
  • Table A1.5 Standard Hard-Disk & Floppy Disk Connectors

    63
  • A1.6 Keyboard Interface

    64
  • Figure A1.6 Keyboard Interface Pinout

    64
  • Table A1.6 Keyboard Connector Signals

    64
  • A1.7 Mouse Interface

    64
  • Figure A1.7 Mouse Interface Pinout

    64
  • Table A1.7 Mouse Connector Signals

    64
  • A1.8 COM1 Interfaces

    65
  • Figure A1.8 COM1 Interface Pinout

    65
  • Table A1.8 COM1 Connector Signals

    65
• ICP-HD Contents

  67
  • B1 ICP-HD CPU Extension

    68
  • B1.1 J11, J13 Interfaces

    68
  • B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)

    68
  • Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU

    68
  • B1.3 IDE Carrier Board ICP-HD-1

    69
  • Figure B1.3 IDE Carrier Board ICP-HD1

    69
  • Table B1.3 ICP-HD-1 Connector Description

    70
  • B1.4 ICP-HDE8MS (Theme Variation)

    70
  • Figure B1.4 IDE Carrier ICP-HDE8MS

    70
  • Table B1.4 IPB-HDE8MS Connector Description

    71
  • B1.5 ICP-HDE8MS Description

    72
  • Figure B1.5 Top & Bottom Views of the ICP-HDE8MS

    72
  • B1.6 Keyboard Interface

    73
  • Figure B1.6 Keyboard Interface Pinout

    73
  • Table B1.6 Keyboard Connector Signals

    73
  • B1.7 Mouse Interface

    73
  • Figure B1.7 Mouse Interface Pinout

    73
  • Table B1.7 Mouse Connector Signals

    73
  • B1.8 COM1 & COM 2 Interfaces

    74
  • Figure B1.8 COM1 & COM2 Interface Pinout

    74
  • Table B1.8 COM1 & COM2 Connector Signals

    74
• IPM-ATA

  75
  • B1 IPM-ATA CPU Extension

    76
  • B1.1 J1 Interfaces

    76
  • Figure B1.1a Dedicated IPM-ATA Backplane

    76
  • B1.1 J1 Interfaces (Contd.)

    77
  • Figure B1.1b The Complete Connection Picture

    77
  • B1.2 IPM-ATA-HD

    78
  • Figure B1.2 IPM-ATA-HD Board Layout

    78
  • Table B1.2 IPM-ATA-HD Jumper Description

    78
  • B1.3 IPM-ATA-CF

    79
  • Figure B1.3 IPM-ATA-CF Board Layout

    79
  • Table B1.3 IPM-ATA-CF Jumper Description

    79
  • B1.4 IPM-ATA-PCMCIA

    80
  • Figure B1.4 IPM-ATA-PCMCIA Board Layout

    80
  • Table B1.4 IPM-ATA-PCMCIA Jumper Description

    80
  • B1.5 Device Compatibility

    81
  • Table B1.5 Compatibility List

    81
• IPB-FPE12 Contents

  83
  • C1 IPB-FPE12 CPU Extension

    84
  • C1.1 J13 Interface for LPT1 & COM2

    84
  • C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)

    84
  • Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU

    84
  • C1.3 LPT1 & COM2 Piggyback

    85
  • Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12

    85
  • Table C1.3 IPB-FPE12 Connector Description

    86
  • C1.4 LPT1 Interface

    87
  • Figure C1.6 LPT1 Interface Pinout

    87
  • Table C1.6 LPT1 Connector Signals

    87
  • C1.5 COM2 Interface

    88
  • Figure C1.5 COM2 Interface Pinout

    88
  • Table C1.5 COM2 Connector Signals

    88
• IPB-RIO Contents

  89
  • D1 IPB-RIO CPU Extension

    90
  • D1.1 IPB-RIO-HD-FD

    90
  • Figure D1.1 IPB-RIO-HD-FD

    90
  • D1.2 IPB-RIO-HD-LPT-(FLEX)

    91
  • Figure D1.2 IPB-RIO-HD-LPT-(FLEX)

    91
  • D1.3 IPB-RIO-C-SHORT

    92
  • Figure D1.3 IPB-RIO-C-SHORT

    92
  • Table D1.3 Rear I/O Type ‘C’

    92
  • D1.4 IPB-RIO-C-80MM

    93
  • Figure D1.4 IPB-RIO-C-80MM

    93