Manuale UtenteSommarioContents3Unpacking and Special Handling Instructions8Revision History9Three Year Limited Warranty101.0 ICP-PIII CPU121.01 Interfacing131.02 Peripherals131.03 Software131.04 Graphics131.1 Specifications141.2 Configuration16Table 1.20 ‘Processor Overview16Figure 1.20 ICP-PIII Overview171.3 Software181.31 Linux181.32 VentureCom181.33 Windows 2000181.34 Windows CE191.35 VxWorks191.36 OS-9 x86191.37 QNX191.38 Jbed191.4 Hardware201.41 Block Diagram20Figure 1.41 Block Diagram201.42 Connector Location21Figure 1.42 Connector Locations211.43 Connector Description21Table 1.43 Connector Description21Table 1.43 Continued221.44 Front-Panel Features22Table 1.44 Front Panels22Figure 1.44 Front-Panel Options231.45 Interface Positions24Figure 1.45 Interfaces242.0 Memory Map26Figure 2.00 System Architecture26Table 2.00 UMB Reservations for ISA27Table 2.01 Port Addressing272.1 I/O Mapped Peripherals28Table 2.10 Legacy I/O Map (ISA Compatible)282.2 Memory Mapped Peripherals292.3 Interrupt Routing29Table 2.30 PC-AT Interrupt Definitions302.4 Inova PIII Device List31Table 2.40 Legacy I/O Map (ISA Compatible)312.5 Interrupt Configuration32Table 2.50 CompactPCI Bus Interrupts322.6 Timer / Counter332.7 Watchdog333.0 CompactPCI J1/J2 Connector373.01 CompactPCI Connector37Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector373.02 ICP-PIII Connector J1 and J237Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment38Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)39Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)40Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)41Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)42Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration433.1 CompactPCI Backplane44Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot453.2 Interfaces463.21 J7 & J12 Fast Ethernet46Figure 3.21 RJ45 Pinout46Table 3.21 Ethernet Connector Signals463.22 J17 VGA Interface47Figure 3.22 High-Density D-Sub VGA Interface Pinout47Table 3.22 Video Output Connector Signals47Table 3.22b Video Resolutions483.23 J16 PanelLink Interface49Figure 3.23 PanelLink Interface Connector49Table 2.12 PanelLink Interface492.24 J16 GigaSTAR Interface50Figure 2.24 GigaSTAR D-Sub Interface Pinout50Table 2.11 GigaSTAR Interface503.25 J19 USB Interface51Figure 3.25 USB Interface Pinout51Table 3.25 USB Connector Signals513.26 J15 FireWire Interface52Figure 3.26 FireWire Interface Pinout52Table 3.26 FireWire Connector Signals523.27 J20 Infrared (iRdA) Interface533.28 J20 Reset Button533.29 J14 FLASH Interface533.30 J18 Floppy Disk Interface533.31 Connecting the PIII to the Inova IPB-FPE854Figure 3.31 CPU to IPB-FPE8 Connection543.32 Connecting the PIII to the Inova ICP-HD-155Figure 3.32 CPU to ICP-HD-1 Connection553.33 Connecting the PIII to the Inova IPB-FPE1256Figure 3.33 CPU to IPB-FPE12 Connection563.34 Connecting the PIII to the Inova IPB-FPE1257Figure 3.34 CPU to IPB-FPE12 Connection573.35 Connecting the PIII to the ICP-FD-158Figure 3.35 CPU to Slim-Line Floppy Disk Connection58A1 IPB-FPE8 CPU Extension60A1.1 J11 Interface for COM1, Mouse & Keyboard60A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)60Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU60A1.3 Stand-Alone IPB-FPE861Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE861A1.4 IPB-FPE8MS (Theme Variation)62Figure A1.4 Piggyback Interface IPB-FPE8MS62Table A1.4 IPB-FPE8MS Connector Description62A1.5 IPB-FPE8MS Description63Figure A1.5 Top & Bottom Views of the IPB-FPE8MS63Table A1.5 Standard Hard-Disk & Floppy Disk Connectors63A1.6 Keyboard Interface64Figure A1.6 Keyboard Interface Pinout64Table A1.6 Keyboard Connector Signals64A1.7 Mouse Interface64Figure A1.7 Mouse Interface Pinout64Table A1.7 Mouse Connector Signals64A1.8 COM1 Interface65Figure A1.8 COM1 Interface Pinout65Table A1.8 COM1 Connector Signals65B1 ICP-HD CPU Extension68B1.1 J11, J13 Interfaces68B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)68Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU68B1.3 IDE Carrier Board ICP-HD-169Figure B1.3 IDE Carrier Board ICP-HD169Table B1.3 ICP-HD-1 Connector Description70B1.4 ICP-HDE8MS (Theme Variation)70Figure B1.4 IDE Carrier ICP-HDE8MS70Table B1.4 IPB-HDE8MS Connector Description71B1.5 ICP-HDE8MS Description72Figure B1.5 Top & Bottom Views of the ICP-HDE8MS72B1.6 Keyboard Interface73Figure B1.6 Keyboard Interface Pinout73Table B1.6 Keyboard Connector Signals73B1.7 Mouse Interface73Figure B1.7 Mouse Interface Pinout73Table B1.7 Mouse Connector Signals73B1.8 COM1 & COM 2 Interfaces74Figure B1.8 COM1 & COM2 Interface Pinout74Table B1.8 COM1 & COM2 Connector Signals74B1 IPM-ATA CPU Extension76B1.1 J1 Interfaces76Figure B1.1a Dedicated IPM-ATA Backplane76B1.1 J1 Interfaces (Contd.)77Figure B1.1b The Complete Connection Picture77B1.2 IPM-ATA-HD78Figure B1.2 IPM-ATA-HD Board Layout78Table B1.2 IPM-ATA-HD Jumper Description78B1.3 IPM-ATA-CF79Figure B1.3 IPM-ATA-CF Board Layout79Table B1.3 IPM-ATA-CF Jumper Description79B1.4 IPM-ATA-PCMCIA80Figure B1.4 IPM-ATA-PCMCIA Board Layout80Table B1.4 IPM-ATA-PCMCIA Jumper Description80B1.5 Device Compatibility81Table B1.5 Compatibility List81C1 IPB-FPE12 CPU Extension84C1.1 J13 Interface for LPT1 & COM284C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)84Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU84C1.3 LPT1 & COM2 Piggyback85Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE1285Table C1.3 IPB-FPE12 Connector Description86C1.4 LPT1 Interface87Figure C1.6 LPT1 Interface Pinout87Table C1.6 LPT1 Connector Signals87C1.5 COM2 Interface88Figure C1.5 COM2 Interface Pinout88Table C1.5 COM2 Connector Signals88D1 IPB-RIO CPU Extension90D1.1 IPB-RIO-HD-FD90Figure D1.1 IPB-RIO-HD-FD90D1.2 IPB-RIO-HD-LPT-(FLEX)91Figure D1.2 IPB-RIO-HD-LPT-(FLEX)91D1.3 IPB-RIO-C-SHORT92Figure D1.3 IPB-RIO-C-SHORT92Table D1.3 Rear I/O Type ‘C’92D1.4 IPB-RIO-C-80MM93Figure D1.4 IPB-RIO-C-80MM93Overview Contents111.0 ICP-PIII CPU121.01 Interfacing131.02 Peripherals131.03 Software131.04 Graphics131.1 Specifications141.2 Configuration16Table 1.20 ‘Processor Overview16Figure 1.20 ICP-PIII Overview171.3 Software181.31 Linux181.32 VentureCom181.33 Windows 2000181.34 Windows CE191.35 VxWorks191.36 OS-9 x86191.37 QNX191.38 Jbed191.4 Hardware201.41 Block Diagram20Figure 1.41 Block Diagram201.42 Connector Location21Figure 1.42 Connector Locations211.43 Connector Description21Table 1.43 Connector Description21Table 1.43 Continued221.44 Front-Panel Features22Table 1.44 Front Panels22Figure 1.44 Front-Panel Options231.45 Interface Positions24Figure 1.45 Interfaces24Configuration Contents252.0 Memory Map26Figure 2.00 System Architecture26Table 2.00 UMB Reservations for ISA27Table 2.01 Port Addressing272.1 I/O Mapped Peripherals28Table 2.10 Legacy I/O Map (ISA Compatible)282.2 Memory Mapped Peripherals292.3 Interrupt Routing29Table 2.30 PC-AT Interrupt Definitions302.4 Inova PIII Device List31Table 2.40 Legacy I/O Map (ISA Compatible)312.5 Interrupt Configuration32Table 2.50 CompactPCI Bus Interrupts322.6 Timer / Counter332.7 Watchdog33Interfaces Contents353.0 CompactPCI J1/J2 Connector373.01 CompactPCI Connector37Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector373.02 ICP-PIII Connector J1 and J237Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment38Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard)39Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A)40Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)41Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C)42Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration433.1 CompactPCI Backplane44Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot453.2 Interfaces463.21 J7 & J12 Fast Ethernet46Figure 3.21 RJ45 Pinout46Table 3.21 Ethernet Connector Signals463.22 J17 VGA Interface47Figure 3.22 High-Density D-Sub VGA Interface Pinout47Table 3.22 Video Output Connector Signals47Table 3.22b Video Resolutions483.23 J16 PanelLink Interface49Figure 3.23 PanelLink Interface Connector49Table 2.12 PanelLink Interface492.24 J16 GigaSTAR Interface50Figure 2.24 GigaSTAR D-Sub Interface Pinout50Table 2.11 GigaSTAR Interface503.25 J19 USB Interface51Figure 3.25 USB Interface Pinout51Table 3.25 USB Connector Signals513.26 J15 FireWire Interface52Figure 3.26 FireWire Interface Pinout52Table 3.26 FireWire Connector Signals523.27 J20 Infrared (iRdA) Interface533.28 J20 Reset Button533.29 J14 FLASH Interface533.30 J18 Floppy Disk Interface533.31 Connecting the PIII to the Inova IPB-FPE854Figure 3.31 CPU to IPB-FPE8 Connection543.32 Connecting the PIII to the Inova ICP-HD-155Figure 3.32 CPU to ICP-HD-1 Connection553.33 Connecting the PIII to the Inova IPB-FPE1256Figure 3.33 CPU to IPB-FPE12 Connection563.34 Connecting the PIII to the Inova IPB-FPE1257Figure 3.34 CPU to IPB-FPE12 Connection573.35 Connecting the PIII to the ICP-FD-158Figure 3.35 CPU to Slim-Line Floppy Disk Connection58IPB-FPE8 Contents59A1 IPB-FPE8 CPU Extension60A1.1 J11 Interface for COM1, Mouse & Keyboard60A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)60Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU60A1.3 Stand-Alone IPB-FPE861Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE861A1.4 IPB-FPE8MS (Theme Variation)62Figure A1.4 Piggyback Interface IPB-FPE8MS62Table A1.4 IPB-FPE8MS Connector Description62A1.5 IPB-FPE8MS Description63Figure A1.5 Top & Bottom Views of the IPB-FPE8MS63Table A1.5 Standard Hard-Disk & Floppy Disk Connectors63A1.6 Keyboard Interface64Figure A1.6 Keyboard Interface Pinout64Table A1.6 Keyboard Connector Signals64A1.7 Mouse Interface64Figure A1.7 Mouse Interface Pinout64Table A1.7 Mouse Connector Signals64A1.8 COM1 Interfaces65Figure A1.8 COM1 Interface Pinout65Table A1.8 COM1 Connector Signals65ICP-HD Contents67B1 ICP-HD CPU Extension68B1.1 J11, J13 Interfaces68B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)68Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU68B1.3 IDE Carrier Board ICP-HD-169Figure B1.3 IDE Carrier Board ICP-HD169Table B1.3 ICP-HD-1 Connector Description70B1.4 ICP-HDE8MS (Theme Variation)70Figure B1.4 IDE Carrier ICP-HDE8MS70Table B1.4 IPB-HDE8MS Connector Description71B1.5 ICP-HDE8MS Description72Figure B1.5 Top & Bottom Views of the ICP-HDE8MS72B1.6 Keyboard Interface73Figure B1.6 Keyboard Interface Pinout73Table B1.6 Keyboard Connector Signals73B1.7 Mouse Interface73Figure B1.7 Mouse Interface Pinout73Table B1.7 Mouse Connector Signals73B1.8 COM1 & COM 2 Interfaces74Figure B1.8 COM1 & COM2 Interface Pinout74Table B1.8 COM1 & COM2 Connector Signals74IPM-ATA75B1 IPM-ATA CPU Extension76B1.1 J1 Interfaces76Figure B1.1a Dedicated IPM-ATA Backplane76B1.1 J1 Interfaces (Contd.)77Figure B1.1b The Complete Connection Picture77B1.2 IPM-ATA-HD78Figure B1.2 IPM-ATA-HD Board Layout78Table B1.2 IPM-ATA-HD Jumper Description78B1.3 IPM-ATA-CF79Figure B1.3 IPM-ATA-CF Board Layout79Table B1.3 IPM-ATA-CF Jumper Description79B1.4 IPM-ATA-PCMCIA80Figure B1.4 IPM-ATA-PCMCIA Board Layout80Table B1.4 IPM-ATA-PCMCIA Jumper Description80B1.5 Device Compatibility81Table B1.5 Compatibility List81IPB-FPE12 Contents83C1 IPB-FPE12 CPU Extension84C1.1 J13 Interface for LPT1 & COM284C1.2 IPB-FPE12 & Front-panel (4HP or 12HP)84Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU84C1.3 LPT1 & COM2 Piggyback85Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE1285Table C1.3 IPB-FPE12 Connector Description86C1.4 LPT1 Interface87Figure C1.6 LPT1 Interface Pinout87Table C1.6 LPT1 Connector Signals87C1.5 COM2 Interface88Figure C1.5 COM2 Interface Pinout88Table C1.5 COM2 Connector Signals88IPB-RIO Contents89D1 IPB-RIO CPU Extension90D1.1 IPB-RIO-HD-FD90Figure D1.1 IPB-RIO-HD-FD90D1.2 IPB-RIO-HD-LPT-(FLEX)91Figure D1.2 IPB-RIO-HD-LPT-(FLEX)91D1.3 IPB-RIO-C-SHORT92Figure D1.3 IPB-RIO-C-SHORT92Table D1.3 Rear I/O Type ‘C’92D1.4 IPB-RIO-C-80MM93Figure D1.4 IPB-RIO-C-80MM93Dimensioni: 3,93 MBPagine: 94Language: EnglishApri il manuale