Benutzerhandbuch für Intel PXA250 and PXA210

Inhaltsverzeichnis

• Intel® PXA250 and PXA210 Applications Processors

  1
• Introduction 1

  9
  • 1.1 Functional Overview

    9
  • 1.2 Package Information

    10
    • 1.2.1 Package Introduction

      10
    • 1.2.2 Signal Pin Descriptions

      12
• System Memory Interface 2

  27
  • 2.1 Overview

    27
  • 2.2 SDRAM Interface

    29
  • 2.3 SDRAM memory wiring diagram

    29
  • 2.4 SDRAM Support

    31
  • 2.5 SDRAM Address Mapping

    32
  • 2.6 Static Memory

    33
    • 2.6.1 Overview

      33
    • 2.6.2 Boot Time Defaults

      34
    • 2.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options

      35
    • 2.6.4 Variable Latency I/O Interface Overview

      35
    • 2.6.5 External Logic for PCMCIA Implementation

      37
    • 2.6.6 DMA / Companion Chip Interface

      40
  • 2.7 System Memory Layout Guidelines

    43
    • 2.7.1 System Memory Topologies (Min and Max Simulated Loading)

      43
    • 2.7.2 System Memory Recommended Trace Lengths

      44
• LCD Display Controller 3

  45
  • 3.1 LCD Display Overview

    45
  • 3.2 Passive (DSTN) Displays

    45
    • 3.2.1 Typical Connections for Passive Panel Displays

      46
      • 3.2.1.1 Passive Monochrome Single Panel Displays

        46
      • 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data

        47
      • 3.2.1.3 Passive Monochrome Dual Panel Displays

        47
      • 3.2.1.4 Passive Color Single Panel Displays

        48
      • 3.2.1.5 Passive Color Dual Panel Displays

        48
  • 3.3 Active (TFT) Displays

    49
    • 3.3.1 Typical connections for Active Panel Displays

      50
  • 3.4 PXA250 Pinout

    51
  • 3.5 Additional Design Considerations

    52
    • 3.5.1 Contrast Voltage

      52
    • 3.5.2 Backlight Inverter

      52
    • 3.5.3 Signal Routing and Buffering

      52
    • 3.5.4 Panel Connector

      53
• USB Interface 4

  55
  • 4.1 Self Powered Device

    55
    • 4.1.1 Operation if GPIOn and GPIOx are Different Pins

      55
    • 4.1.2 Operation if GPIOn and GPIOx are the Same Pin

      56
  • 4.2 Bus Powered Device

    56
• MultiMediaCard (MMC) 5

  57
  • 5.1 Schematics

    57
    • 5.1.1 Signal Description

      57
    • 5.1.2 How to Wire

      58
      • 5.1.2.1 SDCard Socket

        60
      • 5.1.2.2 MMC Socket

        60
    • 5.1.3 Simplified Schematic

      61
    • 5.1.4 Pull-up and Pull-down

      62
  • 5.2 Utilized Features

    62
• AC97 6

  63
  • 6.1 Schematics

    63
  • 6.2 Layout

    64
• I2C 7

  65
  • 7.1 Schematics

    65
    • 7.1.1 Signal Description

      65
    • 7.1.2 Digital-to-Analog Converter (DAC)

      66
    • 7.1.3 Other Uses of I2C

      66
    • 7.1.4 Pull-Ups and Pull-Downs

      67
  • 7.2 Utilized Features

    68
• Power and Clocking 8

  69
  • 8.1 Operating Conditions

    69
  • 8.2 Electrical Specifications

    70
  • 8.3 Power Consumption Specifications

    70
  • 8.4 Oscillator Electrical Specifications

    72
    • 8.4.1 32.768kHz Oscillator Specifications

      72
    • 8.4.2 3.6864MHz Oscillator Specifications

      73
  • 8.5 Reset and Power AC Timing Specifications

    74
    • 8.5.1 Power Supply Connectivity

      74
    • 8.5.2 Power On Timing

      79
    • 8.5.3 Hardware Reset Timing

      80
    • 8.5.4 Watchdog Reset Timing

      81
    • 8.5.5 GPIO Reset Timing

      81
    • 8.5.6 Sleep Mode Timing

      82
  • 8.6 Memory Bus and PCMCIA AC Specifications

    83
  • 8.7 Example Form Factor Reference Design Power Delivery Example

    88
    • 8.7.1 Power System

      88
      • 8.7.1.1 Power System Configuration

        89
    • 8.7.2 CORE Power

      90
    • 8.7.3 PLL Power

      90
    • 8.7.4 I/O 3.3V Power

      91
    • 8.7.5 Peripheral 5.5V Power

      91
• JTAG/Debug Port 9

  93
  • 9.1 Description

    93
  • 9.2 Schematics

    93
  • 9.3 Layout

    94
• SA-1110/Applications Processor Migration A

  95
  • A.1 SA-1110 Hardware Migration Issues

    96
    • A.1.1 Hardware Compatibility

      96
    • A.1.2 Signal Changes

      96
    • A.1.3 Power Delivery

      98
    • A.1.4 Package

      98
    • A.1.5 Clocks

      98
    • A.1.6 UCB1300

      99
  • A.2 SA-1110 to PXA250 Software Migration Issues

    99
    • A.2.1 Software Compatibility

      100
    • A.2.2 Address space

      100
    • A.2.3 Page Table Changes

      100
    • A.2.4 Configuration registers

      100
    • A.2.5 DMA

      101
  • A.3 Using New PXA250 Features

    101
    • A.3.1 Intel® XScale™ Microarchitecture

      102
    • A.3.2 Debugging

      102
    • A.3.3 Cache Attributes

      102
    • A.3.4 Other features

      102
    • A.3.5 Conclusion

      103
• Example Form Factor Reference Design Schematic Diagrams B

  105
  • B.1 Notes

    105
  • B.2 Schematic Diagrams

    105
• BBPXA2xx Development Baseboard Schematic Diagram C

  123
  • C.1 Schematic Diagram

    123
• PXA250 Processor Card Schematic Diagram D

  163
  • D.1 Schematic Diagram

    163
• PXA210 Processor Card Schematic Diagram E

  175
  • E.1 Schematic Diagram

    175