User ManualTable of ContentsIntel® PXA250 and PXA210 Applications Processors1Introduction 191.1 Functional Overview91.2 Package Information101.2.1 Package Introduction101.2.2 Signal Pin Descriptions12System Memory Interface 2272.1 Overview272.2 SDRAM Interface292.3 SDRAM memory wiring diagram292.4 SDRAM Support312.5 SDRAM Address Mapping322.6 Static Memory332.6.1 Overview332.6.2 Boot Time Defaults342.6.3 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options352.6.4 Variable Latency I/O Interface Overview352.6.5 External Logic for PCMCIA Implementation372.6.6 DMA / Companion Chip Interface402.7 System Memory Layout Guidelines432.7.1 System Memory Topologies (Min and Max Simulated Loading)432.7.2 System Memory Recommended Trace Lengths44LCD Display Controller 3453.1 LCD Display Overview453.2 Passive (DSTN) Displays453.2.1 Typical Connections for Passive Panel Displays463.2.1.1 Passive Monochrome Single Panel Displays463.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data473.2.1.3 Passive Monochrome Dual Panel Displays473.2.1.4 Passive Color Single Panel Displays483.2.1.5 Passive Color Dual Panel Displays483.3 Active (TFT) Displays493.3.1 Typical connections for Active Panel Displays503.4 PXA250 Pinout513.5 Additional Design Considerations523.5.1 Contrast Voltage523.5.2 Backlight Inverter523.5.3 Signal Routing and Buffering523.5.4 Panel Connector53USB Interface 4554.1 Self Powered Device554.1.1 Operation if GPIOn and GPIOx are Different Pins554.1.2 Operation if GPIOn and GPIOx are the Same Pin564.2 Bus Powered Device56MultiMediaCard (MMC) 5575.1 Schematics575.1.1 Signal Description575.1.2 How to Wire585.1.2.1 SDCard Socket605.1.2.2 MMC Socket605.1.3 Simplified Schematic615.1.4 Pull-up and Pull-down625.2 Utilized Features62AC97 6636.1 Schematics636.2 Layout64I2C 7657.1 Schematics657.1.1 Signal Description657.1.2 Digital-to-Analog Converter (DAC)667.1.3 Other Uses of I2C667.1.4 Pull-Ups and Pull-Downs677.2 Utilized Features68Power and Clocking 8698.1 Operating Conditions698.2 Electrical Specifications708.3 Power Consumption Specifications708.4 Oscillator Electrical Specifications728.4.1 32.768kHz Oscillator Specifications728.4.2 3.6864MHz Oscillator Specifications738.5 Reset and Power AC Timing Specifications748.5.1 Power Supply Connectivity748.5.2 Power On Timing798.5.3 Hardware Reset Timing808.5.4 Watchdog Reset Timing818.5.5 GPIO Reset Timing818.5.6 Sleep Mode Timing828.6 Memory Bus and PCMCIA AC Specifications838.7 Example Form Factor Reference Design Power Delivery Example888.7.1 Power System888.7.1.1 Power System Configuration898.7.2 CORE Power908.7.3 PLL Power908.7.4 I/O 3.3V Power918.7.5 Peripheral 5.5V Power91JTAG/Debug Port 9939.1 Description939.2 Schematics939.3 Layout94SA-1110/Applications Processor Migration A95A.1 SA-1110 Hardware Migration Issues96A.1.1 Hardware Compatibility96A.1.2 Signal Changes96A.1.3 Power Delivery98A.1.4 Package98A.1.5 Clocks98A.1.6 UCB130099A.2 SA-1110 to PXA250 Software Migration Issues99A.2.1 Software Compatibility100A.2.2 Address space100A.2.3 Page Table Changes100A.2.4 Configuration registers100A.2.5 DMA101A.3 Using New PXA250 Features101A.3.1 Intel® XScale™ Microarchitecture102A.3.2 Debugging102A.3.3 Cache Attributes102A.3.4 Other features102A.3.5 Conclusion103Example Form Factor Reference Design Schematic Diagrams B105B.1 Notes105B.2 Schematic Diagrams105BBPXA2xx Development Baseboard Schematic Diagram C123C.1 Schematic Diagram123PXA250 Processor Card Schematic Diagram D163D.1 Schematic Diagram163PXA210 Processor Card Schematic Diagram E175E.1 Schematic Diagram175Size: 4.76 MBPages: 190Language: EnglishOpen manual