Benutzerhandbuch für LSI 53C810A

Inhaltsverzeichnis

• Chapter1 General Description

  13
  • 1.1 TolerANT® Technology

    14
  • 1.2 LSI53C810A Benefits Summary

    15
    • 1.2.1 SCSI Performance

      15
    • 1.2.2 PCI Performance

      16
    • 1.2.3 Integration

      16
    • 1.2.4 Ease of Use

      16
    • 1.2.5 Flexibility

      17
    • 1.2.6 Reliability

      17
    • 1.2.7 Testability

      18
      • Figure1.1 LSI53C810A System Diagram

        19
      • Figure1.2 LSI53C810A Chip Block Diagram

        20
• Chapter2 Functional Description

  21
  • 2.1 SCSI Core

    21
    • 2.1.1 DMA Core

      22
  • 2.2 SCRIPTS Processor

    22
    • 2.2.1 SDMS Software: The Total SCSI Solution

      23
  • 2.3 Prefetching SCRIPTS Instructions

    23
    • 2.3.1 Opcode Fetch Burst Capability

      24
  • 2.4 PCI Cache Mode

    24
    • 2.4.1 Load and Store Instructions

      25
    • 2.4.2 3.3 V/5 V PCI Interface

      25
    • 2.4.3 Loopback Mode

      25
  • 2.5 Parity Options

    25
    • Table 2.1 Bits Used for Parity Control and Observation

      26
    • Table 2.2 SCSI Parity Control

      27
    • Table 2.3 SCSI Parity Errors and Interrupts

      27
    • 2.5.1 DMA FIFO

      28
      • Figure2.1 DMA FIFO Sections

        28
      • 2.5.1.1 Data Paths

        28
        • Figure2.2 LSI53C810A Host Interface Data Paths

          30
  • 2.6 SCSI Bus Interface

    31
    • 2.6.1 Terminator Networks

      31
    • 2.6.2 Select/Reselect During Selection/Reselection

      31
      • Figure2.3 Active or Regulated Termination

        32
    • 2.6.3 Synchronous Operation

      33
      • 2.6.3.1 Determining the Data Transfer Rate

        33
      • 2.6.3.2 SCNTL3 Register, Bits [6:4] (SCF[2:0])

        33
      • 2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0])

        34
      • 2.6.3.4 SXFER Register, Bits [7:5] (TP[2:0])

        34
      • 2.6.3.5 Achieving Optimal SCSI Send Rates

        34
        • Figure2.4 Determining the Synchronous Transfer Rate

          35
  • 2.7 Interrupt Handling

    35
    • 2.7.1 Polling and Hardware Interrupts

      35
      • 2.7.1.1 Registers

        36
      • 2.7.1.2 Fatal vs. Nonfatal Interrupts

        38
      • 2.7.1.3 Masking

        38
      • 2.7.1.4 Stacked Interrupts

        39
      • 2.7.1.5 Halting in an Orderly Fashion

        40
      • 2.7.1.6 Sample Interrupt Service Routine

        41
• Chapter3 PCI Functional Description

  43
  • 3.1 PCI Addressing

    43
    • 3.1.1 Configuration Space

      43
    • 3.1.2 PCI Bus Commands and Functions Supported

      44
      • 3.1.2.1 I/O Read Command

        44
      • 3.1.2.2 I/O Write Command

        44
      • 3.1.2.3 Memory Read Command

        45
      • 3.1.2.4 Memory Read Multiple Command

        45
      • 3.1.2.5 Memory Read Line Command

        45
      • 3.1.2.6 Memory Write Command

        45
      • 3.1.2.7 Memory Write and Invalidate Command

        45
  • 3.2 PCI Cache Mode

    45
    • 3.2.1 Support for PCI Cache Line Size Register

      45
    • 3.2.2 Selection of Cache Line Size

      46
    • 3.2.3 Alignment

      46
      • 3.2.3.1 MMOV Misalignment

        46
      • 3.2.3.2 Memory Write and Invalidate Command

        47
      • 3.2.3.3 Memory Read Line Command

        48
    • 3.2.4 Memory Read Multiple Command

      49
    • 3.2.5 Unsupported PCI Commands

      50
      • Table 3.1 PCI Bus Commands and Encoding Types

        51
  • 3.3 Configuration Registers

    51
    • Table 3.2 PCI Configuration Register Map

      52
• Chapter4 Signal Descriptions

  63
  • Figure4.1 LSI53C810A Pin Diagram

    64
  • Table 4.1 Power and Ground Signals

    65
  • Figure4.2 Functional Signal Grouping

    66
  • 4.1 PCI Bus Interface Signals

    67
    • 4.1.1 System Signals

      67
      • Table 4.2 System Signals

        67
    • 4.1.2 Address and Data Signals

      68
      • Table 4.3 Address and Data Signals

        68
    • 4.1.3 Interface Control Signals

      69
      • Table 4.4 Interface Control Signals

        69
    • 4.1.4 Arbitration Signals

      70
      • Table 4.5 Arbitration Signals

        70
    • 4.1.5 Error Reporting Signals

      70
      • Table 4.6 Error Reporting Signals

        70
  • 4.2 SCSI Bus Interface Signals

    71
    • 4.2.1 SCSI Bus Interface Signals

      71
      • Table 4.7 SCSI Bus Interface Signals

        71
    • 4.2.2 Additional Interface Signals

      72
      • Table 4.8 Additional Interface Signals

        72
• Chapter5 Operating Registers

  75
  • Figure5.1 Register Address Map

    76
  • Table 5.1 Synchronous Clock Conversion Factor

    84
  • Table 5.2 Asynchronous Clock Conversion Factor

    85
  • Table 5.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1

    87
  • Table 5.4 Examples of Synchronous Transfer Periods and Rates for Fast SCSI

    88
  • Table 5.5 SCSI Synchronous Offset Values

    89
• Chapter6 Instruction Set of the I/O Processor

  141
  • 6.1 Low Level Register Interface Mode

    141
  • 6.2 SCSI SCRIPTS

    142
    • Table 6.1 SCRIPTS Instructions

      143
    • 6.2.1 Sample Operation

      143
      • Figure6.1 SCRIPTS Overview

        145
  • 6.3 Block Move Instructions

    145
    • 6.3.1 First Dword

      146
      • Figure6.2 Block Move Instruction Register

        148
    • 6.3.2 Second Dword

      152
  • 6.4 I/O Instruction

    153
    • 6.4.1 First Dword

      153
      • Figure6.3 I/O Instruction Register

        156
    • 6.4.2 Second Dword

      162
  • 6.5 Read/Write Instructions

    163
    • 6.5.1 First Dword

      163
    • 6.5.2 Second Dword

      163
    • 6.5.3 Read-Modify-Write Cycles

      163
    • 6.5.4 Move To/From SFBR Cycles

      164
      • Figure6.4 Read/Write Register Instruction

        165
      • Table 6.2 Read/Write Instructions

        166
  • 6.6 Transfer Control Instructions

    167
    • 6.6.1 First Dword

      167
      • Figure6.5 Transfer Control Instruction

        170
    • 6.6.2 Second Dword

      175
  • 6.7 Memory Move Instructions

    176
    • Figure6.6 Memory to Memory Move Instruction

      177
    • 6.7.1 First Dword

      178
    • 6.7.2 Second Dword

      178
    • 6.7.3 Third Dword

      178
    • 6.7.4 Read/Write System Memory from a SCRIPTS Instruction

      179
  • 6.8 Load and Store Instructions

    179
    • 6.8.1 First Dword

      180
    • 6.8.2 Second Dword

      181
      • Figure6.7 Load and Store Instruction Format

        182
• Chapter7 Electrical Characteristics

  183
  • 7.1 DC Characteristics

    183
    • Table 7.1 Absolute Maximum Stress Ratings

      184
    • Table 7.2 Operating Conditions

      184
    • Table 7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/

      185
    • Table 7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/

      185
    • Table 7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN

      185
    • Table 7.6 Capacitance

      186
    • Table 7.7 Output Signals—MAC/_TESTOUT, REQ/

      186
    • Table 7.8 Output Signal—IRQ/

      186
    • Table 7.9 Output Signal—SERR/

      187
    • Table 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...

      187
    • Table 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/

      188
  • 7.2 TolerANT Technology

    188
    • Table 7.12 TolerANT Technology Electrical Characteristics

      189
    • Figure7.1 Rise and Fall Time Test Conditions

      190
    • Figure7.2 SCSI Input Filtering

      190
    • Figure7.3 Hysteresis of SCSI Receiver

      190
    • Figure7.4 Input Current as a Function of Input Voltage

      191
    • Figure7.5 Output Current as a Function of Output Voltage

      191
  • 7.3 AC Characteristics

    192
    • Table 7.13 Clock Timing

      192
    • Figure7.6 Clock Timing

      192
    • Table 7.14 Reset Input Timing

      193
    • Figure7.7 Reset Input

      193
    • Table 7.15 Interrupt Output

      193
    • Figure7.8 Interrupt Output Waveforms

      193
  • 7.4 PCI Interface Timing Diagrams

    194
    • 7.4.1 Target Timing

      195
      • Figure7.9 PCI Configuration Register Read

        195
      • Figure7.10 PCI Configuration Register Write

        196
      • Figure7.11 Target Read

        197
      • Figure7.12 Target Write

        198
    • 7.4.2 Initiator Timing

      199
      • Figure7.13 OpCode Fetch, Nonburst

        199
      • Figure7.14 Burst Opcode Fetch

        200
      • Figure7.15 Back-to-Back Read

        201
      • Figure7.16 Back-to-Back Write

        202
      • Figure7.17 Burst Read

        204
      • Figure7.18 Burst Write

        206
  • 7.5 PCI Interface Timing

    208
    • Table 7.16 PCI Timing

      208
  • 7.6 SCSI Timings

    209
    • Table 7.17 Initiator Asynchronous Send (5 Mbytes/s)

      209
    • Figure7.19 Initiator Asynchronous Send

      209
    • Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s)

      210
    • Figure7.20 Initiator Asynchronous Receive

      210
    • Table 7.19 Target Asynchronous Send (5 Mbytes/s)

      211
    • Figure7.21 Target Asynchronous Send

      211
    • Table 7.20 Target Asynchronous Receive (5 Mbytes/s)

      212
    • Figure7.22 Target Asynchronous Receive

      212
    • Figure7.23 Initiator and Target Synchronous Transfers

      212
    • Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s)

      213
    • Table 7.22 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 40 MHz Clock)

      213
    • Table 7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock)

      214
  • 7.7 Package Drawings

    215
    • Figure7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2)

      216
• AppendixA Register Summary

  219
  • TableA.1 Configuration Registers

    219
  • TableA.2 SCSI Registers

    220
• Index

  223
• Customer Feedback

  231