LSI 53C810A マニュアル

目次

• Chapter1 General Description

  13
  • 1.1 TolerANT® Technology

    14
  • 1.2 LSI53C810A Benefits Summary

    15
    • 1.2.1 SCSI Performance

      15
    • 1.2.2 PCI Performance

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    • 1.2.3 Integration

      16
    • 1.2.4 Ease of Use

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    • 1.2.5 Flexibility

      17
    • 1.2.6 Reliability

      17
    • 1.2.7 Testability

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      • Figure1.1 LSI53C810A System Diagram

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      • Figure1.2 LSI53C810A Chip Block Diagram

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• Chapter2 Functional Description

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  • 2.1 SCSI Core

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    • 2.1.1 DMA Core

      22
  • 2.2 SCRIPTS Processor

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    • 2.2.1 SDMS Software: The Total SCSI Solution

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  • 2.3 Prefetching SCRIPTS Instructions

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    • 2.3.1 Opcode Fetch Burst Capability

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  • 2.4 PCI Cache Mode

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    • 2.4.1 Load and Store Instructions

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    • 2.4.2 3.3 V/5 V PCI Interface

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    • 2.4.3 Loopback Mode

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  • 2.5 Parity Options

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    • Table 2.1 Bits Used for Parity Control and Observation

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    • Table 2.2 SCSI Parity Control

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    • Table 2.3 SCSI Parity Errors and Interrupts

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    • 2.5.1 DMA FIFO

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      • Figure2.1 DMA FIFO Sections

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      • 2.5.1.1 Data Paths

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        • Figure2.2 LSI53C810A Host Interface Data Paths

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  • 2.6 SCSI Bus Interface

    31
    • 2.6.1 Terminator Networks

      31
    • 2.6.2 Select/Reselect During Selection/Reselection

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      • Figure2.3 Active or Regulated Termination

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    • 2.6.3 Synchronous Operation

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      • 2.6.3.1 Determining the Data Transfer Rate

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      • 2.6.3.2 SCNTL3 Register, Bits [6:4] (SCF[2:0])

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      • 2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0])

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      • 2.6.3.4 SXFER Register, Bits [7:5] (TP[2:0])

        34
      • 2.6.3.5 Achieving Optimal SCSI Send Rates

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        • Figure2.4 Determining the Synchronous Transfer Rate

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  • 2.7 Interrupt Handling

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    • 2.7.1 Polling and Hardware Interrupts

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      • 2.7.1.1 Registers

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      • 2.7.1.2 Fatal vs. Nonfatal Interrupts

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      • 2.7.1.3 Masking

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      • 2.7.1.4 Stacked Interrupts

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      • 2.7.1.5 Halting in an Orderly Fashion

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      • 2.7.1.6 Sample Interrupt Service Routine

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• Chapter3 PCI Functional Description

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  • 3.1 PCI Addressing

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    • 3.1.1 Configuration Space

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    • 3.1.2 PCI Bus Commands and Functions Supported

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      • 3.1.2.1 I/O Read Command

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      • 3.1.2.2 I/O Write Command

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      • 3.1.2.3 Memory Read Command

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      • 3.1.2.4 Memory Read Multiple Command

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      • 3.1.2.5 Memory Read Line Command

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      • 3.1.2.6 Memory Write Command

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      • 3.1.2.7 Memory Write and Invalidate Command

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  • 3.2 PCI Cache Mode

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    • 3.2.1 Support for PCI Cache Line Size Register

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    • 3.2.2 Selection of Cache Line Size

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    • 3.2.3 Alignment

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      • 3.2.3.1 MMOV Misalignment

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      • 3.2.3.2 Memory Write and Invalidate Command

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      • 3.2.3.3 Memory Read Line Command

        48
    • 3.2.4 Memory Read Multiple Command

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    • 3.2.5 Unsupported PCI Commands

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      • Table 3.1 PCI Bus Commands and Encoding Types

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  • 3.3 Configuration Registers

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    • Table 3.2 PCI Configuration Register Map

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• Chapter4 Signal Descriptions

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  • Figure4.1 LSI53C810A Pin Diagram

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  • Table 4.1 Power and Ground Signals

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  • Figure4.2 Functional Signal Grouping

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  • 4.1 PCI Bus Interface Signals

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    • 4.1.1 System Signals

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      • Table 4.2 System Signals

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    • 4.1.2 Address and Data Signals

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      • Table 4.3 Address and Data Signals

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    • 4.1.3 Interface Control Signals

      69
      • Table 4.4 Interface Control Signals

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    • 4.1.4 Arbitration Signals

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      • Table 4.5 Arbitration Signals

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    • 4.1.5 Error Reporting Signals

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      • Table 4.6 Error Reporting Signals

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  • 4.2 SCSI Bus Interface Signals

    71
    • 4.2.1 SCSI Bus Interface Signals

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      • Table 4.7 SCSI Bus Interface Signals

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    • 4.2.2 Additional Interface Signals

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      • Table 4.8 Additional Interface Signals

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• Chapter5 Operating Registers

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  • Figure5.1 Register Address Map

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  • Table 5.1 Synchronous Clock Conversion Factor

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  • Table 5.2 Asynchronous Clock Conversion Factor

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  • Table 5.3 Examples of Synchronous Transfer Periods and Rates for SCSI-1

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  • Table 5.4 Examples of Synchronous Transfer Periods and Rates for Fast SCSI

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  • Table 5.5 SCSI Synchronous Offset Values

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• Chapter6 Instruction Set of the I/O Processor

  141
  • 6.1 Low Level Register Interface Mode

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  • 6.2 SCSI SCRIPTS

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    • Table 6.1 SCRIPTS Instructions

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    • 6.2.1 Sample Operation

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      • Figure6.1 SCRIPTS Overview

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  • 6.3 Block Move Instructions

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    • 6.3.1 First Dword

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      • Figure6.2 Block Move Instruction Register

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    • 6.3.2 Second Dword

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  • 6.4 I/O Instruction

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    • 6.4.1 First Dword

      153
      • Figure6.3 I/O Instruction Register

        156
    • 6.4.2 Second Dword

      162
  • 6.5 Read/Write Instructions

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    • 6.5.1 First Dword

      163
    • 6.5.2 Second Dword

      163
    • 6.5.3 Read-Modify-Write Cycles

      163
    • 6.5.4 Move To/From SFBR Cycles

      164
      • Figure6.4 Read/Write Register Instruction

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      • Table 6.2 Read/Write Instructions

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  • 6.6 Transfer Control Instructions

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    • 6.6.1 First Dword

      167
      • Figure6.5 Transfer Control Instruction

        170
    • 6.6.2 Second Dword

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  • 6.7 Memory Move Instructions

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    • Figure6.6 Memory to Memory Move Instruction

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    • 6.7.1 First Dword

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    • 6.7.2 Second Dword

      178
    • 6.7.3 Third Dword

      178
    • 6.7.4 Read/Write System Memory from a SCRIPTS Instruction

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  • 6.8 Load and Store Instructions

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    • 6.8.1 First Dword

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    • 6.8.2 Second Dword

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      • Figure6.7 Load and Store Instruction Format

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• Chapter7 Electrical Characteristics

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  • 7.1 DC Characteristics

    183
    • Table 7.1 Absolute Maximum Stress Ratings

      184
    • Table 7.2 Operating Conditions

      184
    • Table 7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/

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    • Table 7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/

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    • Table 7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN

      185
    • Table 7.6 Capacitance

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    • Table 7.7 Output Signals—MAC/_TESTOUT, REQ/

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    • Table 7.8 Output Signal—IRQ/

      186
    • Table 7.9 Output Signal—SERR/

      187
    • Table 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...

      187
    • Table 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/

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  • 7.2 TolerANT Technology

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    • Table 7.12 TolerANT Technology Electrical Characteristics

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    • Figure7.1 Rise and Fall Time Test Conditions

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    • Figure7.2 SCSI Input Filtering

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    • Figure7.3 Hysteresis of SCSI Receiver

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    • Figure7.4 Input Current as a Function of Input Voltage

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    • Figure7.5 Output Current as a Function of Output Voltage

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  • 7.3 AC Characteristics

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    • Table 7.13 Clock Timing

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    • Figure7.6 Clock Timing

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    • Table 7.14 Reset Input Timing

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    • Figure7.7 Reset Input

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    • Table 7.15 Interrupt Output

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    • Figure7.8 Interrupt Output Waveforms

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  • 7.4 PCI Interface Timing Diagrams

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    • 7.4.1 Target Timing

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      • Figure7.9 PCI Configuration Register Read

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      • Figure7.10 PCI Configuration Register Write

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      • Figure7.11 Target Read

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      • Figure7.12 Target Write

        198
    • 7.4.2 Initiator Timing

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      • Figure7.13 OpCode Fetch, Nonburst

        199
      • Figure7.14 Burst Opcode Fetch

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      • Figure7.15 Back-to-Back Read

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      • Figure7.16 Back-to-Back Write

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      • Figure7.17 Burst Read

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      • Figure7.18 Burst Write

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  • 7.5 PCI Interface Timing

    208
    • Table 7.16 PCI Timing

      208
  • 7.6 SCSI Timings

    209
    • Table 7.17 Initiator Asynchronous Send (5 Mbytes/s)

      209
    • Figure7.19 Initiator Asynchronous Send

      209
    • Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s)

      210
    • Figure7.20 Initiator Asynchronous Receive

      210
    • Table 7.19 Target Asynchronous Send (5 Mbytes/s)

      211
    • Figure7.21 Target Asynchronous Send

      211
    • Table 7.20 Target Asynchronous Receive (5 Mbytes/s)

      212
    • Figure7.22 Target Asynchronous Receive

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    • Figure7.23 Initiator and Target Synchronous Transfers

      212
    • Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s)

      213
    • Table 7.22 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 40 MHz Clock)

      213
    • Table 7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock)

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  • 7.7 Package Drawings

    215
    • Figure7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2)

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• AppendixA Register Summary

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  • TableA.1 Configuration Registers

    219
  • TableA.2 SCSI Registers

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• Index

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• Customer Feedback

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