Benutzerhandbuch für Nortel Networks MSC8101 ADS

Inhaltsverzeichnis

• 1 - General Information

  11
  • 1•1 Introduction

    11
  • 1•2 Abbreviations’ List

    11
  • 1•3 Related Documentation

    11
  • 1•4 Specification

    12
    • TABLE 1-1. MSC8101ADS Specifications

      12
  • 1•5 ADS Features

    13
    • FIGURE 1-1 MSC8101ADS Block Diagram

      15
• 2 - Hardware Preparation

  16
  • 2•1 INTRODUCTION

    16
  • 2•2 UNPACKING INSTRUCTIONS

    16
  • 2•3 HARDWARE PREPARATION

    16
    • FIGURE 2-1 MSC8101ADS Top Side Part Location diagram

      17
• 3 - Installation Instructions

  19
  • 3•1 OnCE Connection Scheme

    19
    • FIGURE 3-1 Host System Debug Scheme A

      19
  • 3•2 Host I/F Operation

    19
    • FIGURE 3-2 Host System Debug Scheme B

      20
  • 3•3 Stand Alone Operation

    20
    • FIGURE 3-3 Stand Alone Configuration

      21
  • 3•4 +5V Power Supply Connection

    21
    • FIGURE 3-4 P26: +5V Power Connector

      21
  • 3•5 JTAG/OnCE Connector - P6

    21
    • FIGURE 3-5 P6 - JTAG/OnCE Port Connector

      22
  • 3•6 HOST I/F Connector - P4

    22
    • FIGURE 3-6 P4 - Host I/F Connector

      23
  • 3•7 Terminal to MSC8101ADS RS-232 Connection

    23
    • FIGURE 3-7 P27A - Upper RS-232 Serial Port Connector

      24
    • FIGURE 3-8 P27B - Lower RS-232 Serial Port Connector

      24
  • 3•8 10/100-Base-T Ethernet Port Connection

    24
  • 3•9 Flash Memory SIMM Installation

    24
  • CAUTION

    25
    • FIGURE 3-9 Flash Memory SIMM Insertion

      25
• 4 - Operating Instructions

  26
  • 4•1 INTRODUCTION

    26
  • 4•2 SWITCHES

    26
    • FIGURE 4-1 Switch SW1 HOST - Description

      26
    • FIGURE 4-2 Switch SW2 - Description

      27
    • FIGURE 4-3 DIP-Switch 64/32 Bit Setting

      28
    • FIGURE 4-4 Switch SW9 MODCK - Description

      29
    • TABLE 4-1. Available Clock Mode Setting

      29
    • FIGURE 4-5 Switch SW10 BOOT MODE - Description

      30
    • FIGURE 4-6 Switch SW11 S/W Option - Description

      30
  • 4•3 Jumpers

    30
    • TABLE 4-2. JP1/JP2 Settings

      31
    • FIGURE 4-7 JP4 - FLASH Programming Source Selection

      31
    • FIGURE 4-8 JP9 - 5V CODEC Source Selection

      32
  • 4•4 LEDs

    32
  • 4•5 The MSC8101’s Registers’ Programming

    34
    • TABLE 4-3. SIU Registers’ Programming

      35
    • TABLE 4-4. Memory Controller Initialization for 100(50) MHz

      36
• 5 - Functional Description

  39
  • 5•1 Reset & Reset - Configuration

    39
    • TABLE 5-1 Summary Reset Configuration Schemes.

      40
    • TABLE 5-2. Hard Reset Configuration Word

      40
  • 5•2 Local Interrupter

    42
  • 5•3 Clock Generator

    42
    • FIGURE 5-1 Clock Distribution Scheme

      43
  • 5•4 Bus Buffering

    43
  • 5•5 Chip - Select Generator

    43
    • TABLE 5-3. MSC8101ADS Chip Select Assignments

      44
  • 5•6 Synchronous DRAM Bank

    44
    • FIGURE 5-2 SDRAM Connection Scheme

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    • TABLE 5-4. 100 MHz SDRAM Mode Register Programming

      45
  • 5•7 Flash Memory SIMM

    46
    • TABLE 5-5. Flash Memory Projected Performance Figures

      46
    • FIGURE 5-3 FLASH SIMM Connection Scheme

      47
  • 5•8 Communication Ports

    48
    • TABLE 5-6. Ports Function Enable

      49
    • FIGURE 5-4 MSC8101 to CODEC connection.

      51
    • TABLE 5-7. CS4221 Programming

      51
    • FIGURE 5-5 RS232 Serial Ports’ Connector

      52
  • 5•9 Host I/F

    53
    • FIGURE 5-6 Host Interface Diagram

      53
    • TABLE 5-8. Host I/F Interconnect signals

      54
  • 5•10 DMA off-board tool

    54
  • 5•11 Board Control & Status Register - BCSR

    54
    • TABLE 5-9. BCSR0 Description

      55
    • TABLE 5-10. BCSR1 Description

      56
    • TABLE 5-11. Peripheral’s Availability Decoding.

      58
    • TABLE 5-12. BCSR2 Description

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    • TABLE 5-13. Flash Presence Detect (7:5) Encoding

      59
    • TABLE 5-14. Flash Presence Detect (4:1) Encoding

      59
    • TABLE 5-15. BCSR3 Description

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    • TABLE 5-16. EXTOOLI(0:3) Assignment

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    • TABLE 5-17. External Tool Revision Encoding

      61
    • TABLE 5-18. ADS Revision Encoding

      61
• 6 - PPC Bus Memory Map

  62
  • TABLE 6-1. MSC8101ADS Memory Map

    63
• 7 - Power

  65
  • 7•1 Power rails.

    65
    • FIGURE 7-1 ADS Power Scheme

      65
    • TABLE 7-1. Off-Board Application Maximum Current Consumption

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• APPENDIX A - MSC8101 Bill of Material

  67
  • A•1 BOM

    68
    • TABLE A-1. MSC8101ADS Bill Of Material

      68
• APPENDIX B - Support Information

  76
  • B•1 Interconnect Signals

    77
    • TABLE B1-2. P1 - System Expansion - Interconnect Signals

      78
    • TABLE B1-3. P2 - CPM Expansion - Interconnect Signals

      83
    • TABLE B1-4. P3 - ISP Connector - Interconnect Signals

      91
    • TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals

      91
    • TABLE B1-6. P6 - JTAG/ONCE Connector - Interconnect Signals

      93
    • TABLE B1-7. P12 - Ethernet Port Interconnect Signals

      94
    • TABLE B1-8. P17,P18 - T1/E1 Line Connectors Interconnect Signals

      95
    • TABLE B1-9. P19,P21,P24 - Stereo Phone Connectors Interconnect Signals

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    • TABLE B1-10. P27A Interconnect Signals

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    • TABLE B1-11. P27B Interconnect Signals

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• APPENDIX C - Program Information

  98
  • C•1 Logic Equations

    100