User ManualTable of Contents1 - General Information111•1 Introduction111•2 Abbreviations’ List111•3 Related Documentation111•4 Specification12TABLE 1-1. MSC8101ADS Specifications121•5 ADS Features13FIGURE 1-1 MSC8101ADS Block Diagram152 - Hardware Preparation162•1 INTRODUCTION162•2 UNPACKING INSTRUCTIONS162•3 HARDWARE PREPARATION16FIGURE 2-1 MSC8101ADS Top Side Part Location diagram173 - Installation Instructions193•1 OnCE Connection Scheme19FIGURE 3-1 Host System Debug Scheme A193•2 Host I/F Operation19FIGURE 3-2 Host System Debug Scheme B203•3 Stand Alone Operation20FIGURE 3-3 Stand Alone Configuration213•4 +5V Power Supply Connection21FIGURE 3-4 P26: +5V Power Connector213•5 JTAG/OnCE Connector - P621FIGURE 3-5 P6 - JTAG/OnCE Port Connector223•6 HOST I/F Connector - P422FIGURE 3-6 P4 - Host I/F Connector233•7 Terminal to MSC8101ADS RS-232 Connection23FIGURE 3-7 P27A - Upper RS-232 Serial Port Connector24FIGURE 3-8 P27B - Lower RS-232 Serial Port Connector243•8 10/100-Base-T Ethernet Port Connection243•9 Flash Memory SIMM Installation24CAUTION25FIGURE 3-9 Flash Memory SIMM Insertion254 - Operating Instructions264•1 INTRODUCTION264•2 SWITCHES26FIGURE 4-1 Switch SW1 HOST - Description26FIGURE 4-2 Switch SW2 - Description27FIGURE 4-3 DIP-Switch 64/32 Bit Setting28FIGURE 4-4 Switch SW9 MODCK - Description29TABLE 4-1. Available Clock Mode Setting29FIGURE 4-5 Switch SW10 BOOT MODE - Description30FIGURE 4-6 Switch SW11 S/W Option - Description304•3 Jumpers30TABLE 4-2. JP1/JP2 Settings31FIGURE 4-7 JP4 - FLASH Programming Source Selection31FIGURE 4-8 JP9 - 5V CODEC Source Selection324•4 LEDs324•5 The MSC8101’s Registers’ Programming34TABLE 4-3. SIU Registers’ Programming35TABLE 4-4. Memory Controller Initialization for 100(50) MHz365 - Functional Description395•1 Reset & Reset - Configuration39TABLE 5-1 Summary Reset Configuration Schemes.40TABLE 5-2. Hard Reset Configuration Word405•2 Local Interrupter425•3 Clock Generator42FIGURE 5-1 Clock Distribution Scheme435•4 Bus Buffering435•5 Chip - Select Generator43TABLE 5-3. MSC8101ADS Chip Select Assignments445•6 Synchronous DRAM Bank44FIGURE 5-2 SDRAM Connection Scheme45TABLE 5-4. 100 MHz SDRAM Mode Register Programming455•7 Flash Memory SIMM46TABLE 5-5. Flash Memory Projected Performance Figures46FIGURE 5-3 FLASH SIMM Connection Scheme475•8 Communication Ports48TABLE 5-6. Ports Function Enable49FIGURE 5-4 MSC8101 to CODEC connection.51TABLE 5-7. CS4221 Programming51FIGURE 5-5 RS232 Serial Ports’ Connector525•9 Host I/F53FIGURE 5-6 Host Interface Diagram53TABLE 5-8. Host I/F Interconnect signals545•10 DMA off-board tool545•11 Board Control & Status Register - BCSR54TABLE 5-9. BCSR0 Description55TABLE 5-10. BCSR1 Description56TABLE 5-11. Peripheral’s Availability Decoding.58TABLE 5-12. BCSR2 Description58TABLE 5-13. Flash Presence Detect (7:5) Encoding59TABLE 5-14. Flash Presence Detect (4:1) Encoding59TABLE 5-15. BCSR3 Description60TABLE 5-16. EXTOOLI(0:3) Assignment61TABLE 5-17. External Tool Revision Encoding61TABLE 5-18. ADS Revision Encoding616 - PPC Bus Memory Map62TABLE 6-1. MSC8101ADS Memory Map637 - Power657•1 Power rails.65FIGURE 7-1 ADS Power Scheme65TABLE 7-1. Off-Board Application Maximum Current Consumption66APPENDIX A - MSC8101 Bill of Material67A•1 BOM68TABLE A-1. MSC8101ADS Bill Of Material68APPENDIX B - Support Information76B•1 Interconnect Signals77TABLE B1-2. P1 - System Expansion - Interconnect Signals78TABLE B1-3. P2 - CPM Expansion - Interconnect Signals83TABLE B1-4. P3 - ISP Connector - Interconnect Signals91TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals91TABLE B1-6. P6 - JTAG/ONCE Connector - Interconnect Signals93TABLE B1-7. P12 - Ethernet Port Interconnect Signals94TABLE B1-8. P17,P18 - T1/E1 Line Connectors Interconnect Signals95TABLE B1-9. P19,P21,P24 - Stereo Phone Connectors Interconnect Signals95TABLE B1-10. P27A Interconnect Signals96TABLE B1-11. P27B Interconnect Signals96APPENDIX C - Program Information98C•1 Logic Equations100Size: 1.77 MBPages: 119Language: EnglishOpen manual