Benutzerhandbuch für Texas Instruments IC MCU 16B MSP430F2410TRGCT VQFN-64 TID

Inhaltsverzeichnis

• FEATURES

  1
• DESCRIPTION

  2
  • Development Tool Support

    2
  • Device Pinout, MSP430F23x

    3
  • Device Pinout, MSP430F24x, MSP430F2410

    4
  • Device Pinout, MSP430F24x1

    5
  • Functional Block Diagram, MSP430F23x

    6
  • Functional Block Diagram, MSP430F24x, MSP430F2410

    7
  • Functional Block Diagram, MSP430F24x1

    8
• SHORT-FORM DESCRIPTION

  15
  • CPU

    15
  • Instruction Set

    15
  • Operating Modes

    16
  • Interrupt Vector Addresses

    17
  • Special Function Registers

    18
  • Memory Organization

    19
  • Bootstrap Loader (BSL)

    19
  • Flash Memory

    19
  • Peripherals

    21
  • Oscillator and System Clock

    21
  • Calibration Data Stored in Information Memory Segment A

    21
  • Brownout, Supply Voltage Supervisor (SVS)

    21
  • Digital I/O

    22
  • Watchdog Timer (WDT+)

    22
  • Hardware Multiplier

    22
  • Timer_A3

    22
  • Timer_B7 (MSP430F24x(1) and MSP430F2410 Devices)

    23
  • Timer_B3 (MSP430F23x Devices)

    24
  • Universal Serial Communications Interface (USCI)

    24
  • Comparator_A+

    24
  • ADC12 (MSP430F23x, MSP430F24x, and MSP430F2410 Devices)

    24
  • Peripheral File Map

    25
• Absolute Maximum Ratings

  30
• Recommended Operating Conditions

  30
• Active Mode Supply Current (Into DVCC and AVCC) Excluding External Current

  31
  • Typical Characteristics - Active-Mode Supply Current (Into DVCC and AVCC )

    32
• Low-Power-Mode Supply Currents (Into VCC) Excluding External Current

  33
• Typical Characteristics - LPM4 Current

  34
• Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG, XIN, XT2IN)

  35
• Inputs (Ports P1, P2)

  35
• Leakage Current (Ports P1, P2, P3, P4, P5, P6)

  35
• Standard Inputs (RST/NMI)

  35
• Outputs (Ports P1, P2, P3, P4, P5, P6)

  36
• Output Frequency (Ports P1, P2, P3, P4, P5, P6)

  36
• Typical Characteristics - Outputs

  37
• POR and Brownout Reset (BOR)

  38
• Typical Characteristics - POR/Brownout Reset (BOR)

  39
• SVS (Supply Voltage Supervisor and Supply Voltage Monitor)

  40
  • Main DCO Characteristics

    42
• DCO Frequency

  42
• Calibrated DCO Frequencies - Tolerance at Calibration

  43
• Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C

  43
• Calibrated DCO Frequencies - Tolerance Over Supply Voltage VCC

  44
• Calibrated DCO Frequencies - Overall Tolerance

  44
• Typical Characteristics - Calibrated DCO Frequency

  45
• Wake-Up From Lower-Power Modes (LPM3/4)

  46
• Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4

  46
• DCO With External Resistor ROSC

  47
• Typical Characteristics - DCO With External Resistor ROSC

  47
• Crystal Oscillator LFXT1, Low-Frequency Mode

  48
• Internal Very-Low-Power Low-Frequency Oscillator (VLO)

  48
• Crystal Oscillator LFXT1, High-Frequency Mode

  49
• Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)

  50
• Crystal Oscillator XT2

  51
• Typical Characteristics - XT2 Oscillator

  52
• Timer_A

  53
• Timer_B

  53
• USCI (UART Mode)

  54
• USCI (SPI Master Mode)

  54
• USCI (SPI Slave Mode)

  54
• USCI (I2C Mode)

  57
• Comparator_A+

  58
• Typical Characteristics, Comparator_A+

  60
• 12-bit ADC, Power Supply and Input Range Conditions

  61
• 12-Bit ADC, External Reference

  61
• 12-Bit ADC, Built-In Reference

  62
• 12-Bit ADC, Timing Parameters

  64
• 12-Bit ADC, Linearity Parameters

  64
• 12-Bit ADC, Temperature Sensor and Built-In VMID

  65
• Flash Memory

  66
• RAM

  66
• JTAG Interface

  66
• JTAG Fuse

  66
• APPLICATION INFORMATION

  67
  • Port P1 Pin Schematic: P1.0 to P1.7, Input/Output With Schmitt Trigger

    67
  • Port P2 Pin Schematic: P2.0 to P2.4, P2.6, and P2.7, Input/Output With Schmitt Trigger

    69
  • Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger

    71
  • Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger

    72
  • Port P4 Pin Schematic: P4.0 to P4.7, Input/Output With Schmitt Trigger

    73
  • Port P5 Pin Schematic: P5.0 to P5.3, Input/Output With Schmitt Trigger

    74
  • Port P5 Pin Schematic: P5.4 to P5.7, Input/Output With Schmitt Trigger

    75
  • Port P6 Pin Schematic: P6.0 to P6.6, Input/Output With Schmitt Trigger

    76
  • Port P6 Pin Schematic: P6.7, Input/Output With Schmitt Trigger

    77
  • JTAG Pins (TMS, TCK, TDI/TCLK, TDO/TDI), Input/Output With Schmitt Trigger

    78
  • JTAG Fuse Check Mode

    79
• Revision History

  80