BenutzerhandbuchInhaltsverzeichnisTable of Contents3Preface91 Introduction111.1 Introduction121.2 Block Diagram121.3 DSP Subsystem in TMS320DM643x DMP131.3.1 Components of the DSP Subsystem132 TMS320C64x+ Megamodule152.1 Introduction162.2 TMS320C64x+ CPU162.3 Memory Controllers182.3.1 L1P Controller182.3.2 L1D Controller202.3.3 L2 Controller202.3.4 External Memory Controller (EMC)212.3.5 Internal DMA (IDMA)212.4 Internal Peripherals222.4.1 Interrupt Controller (INTC)222.4.2 Power-Down Controller (PDC)222.4.3 Bandwidth Manager233 System Memory253.1 Memory Map263.1.1 DSP Internal Memory (L1P, L1D, L2)263.1.2 External Memory263.1.3 Internal Peripherals263.1.4 Device Peripherals263.2 Memory Interfaces Overview273.2.1 DDR2 External Memory Interface273.2.2 External Memory Interface273.2.2.1 Asynchronous EMIF Interface273.2.2.2 NAND Interface274 Device Clocking294.1 Overview304.2 Clock Domains304.2.1 Core Domains304.2.2 Core Frequency Flexibility324.2.3 DDR2/EMIF Clock334.2.4 I/O Domains344.2.5 Video Processing Back End355 PLL Controller375.1 PLL Module385.2 PLL1 Control385.2.1 Device Clock Generation395.2.2 Steps for Changing PLL1/Core Domain Frequency395.2.2.1 Initialization to PLL Mode from PLL Power Down405.2.2.2 Changing PLL Multiplier415.2.2.3 Changing SYSCLK Dividers425.3 PLL2 Control435.3.1 Device Clock Generation435.3.2 Steps for Changing PLL2 Frequency445.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency445.3.2.1.1 PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset445.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset445.3.2.2 Initialization to PLL Mode from PLL Power Down455.3.2.3 Changing PLL Multiplier465.3.2.4 Changing SYSCLK Dividers475.4 PLL Controller Registers485.4.1 Peripheral ID Register (PID)495.4.2 Reset Type Status Register (RSTYPE)495.4.3 PLL Control Register (PLLCTL)505.4.4 PLL Multiplier Control Register (PLLM)515.4.5 PLL Controller Divider 1 Register (PLLDIV1)515.4.6 PLL Controller Divider 2 Register (PLLDIV2)525.4.7 PLL Controller Divider 3 Register (PLLDIV3)525.4.8 Oscillator Divider 1 Register (OSCDIV1)535.4.9 Bypass Divider Register (BPDIV)545.4.10 PLL Controller Command Register (PLLCMD)555.4.11 PLL Controller Status Register (PLLSTAT)555.4.12 PLL Controller Clock Align Control Register (ALNCTL)565.4.13 PLLDIV Ratio Change Status Register (DCHANGE)575.4.14 Clock Enable Control Register (CKEN)585.4.15 Clock Status Register (CKSTAT)595.4.16 SYSCLK Status Register (SYSTAT)606 Power and Sleep Controller616.1 Introduction626.2 Power Domain and Module Topology636.3 Power Domain and Module States646.3.1 Power Domain States646.3.2 Module States646.3.3 Local Reset656.4 Executing State Transitions656.4.1 Power Domain State Transitions656.4.2 Module State Transitions656.5 IcePick Emulation Support in the PSC666.6 PSC Interrupts666.6.1 Interrupt Events666.6.1.1 Module State Emulation Events676.6.1.2 Local Reset Emulation Events676.6.2 Interrupt Registers676.6.3 Interrupt Handling686.7 PSC Registers686.7.1 Peripheral Revision and Class Information Register (PID)696.7.2 Interrupt Evaluation Register (INTEVAL)696.7.3 Module Error Pending Register 1 (MERRPR1)706.7.4 Module Error Clear Register 1 (MERRCR1)706.7.5 Power Domain Transition Command Register (PTCMD)716.7.6 Power Domain Transition Status Register (PTSTAT)716.7.7 Power Domain Status 0 Register (PDSTAT0)726.7.8 Power Domain Control 0 Register (PDCTL0)736.7.9 Module Status n Register (MDSTATn)746.7.10 Module Control n Register (MDCTLn)757 Power Management777.1 Overview787.2 PSC and PLLC Overview787.3 Clock Management797.3.1 Module Clock ON/OFF797.3.2 Module Clock Frequency Scaling797.3.3 PLL Bypass and Power Down797.4 DSP Sleep Mode Management807.4.1 DSP Sleep Modes807.4.2 DSP Module Clock ON/OFF807.4.2.1 DSP Module Clock ON807.4.2.2 DSP Module Clock Off817.5 3.3 V I/O Power Down817.6 Video DAC Power Down818 Interrupt Controller839 System Module859.1 Overview869.2 Device Identification869.3 Device Configuration869.3.1 Pin Multiplexing Control869.3.2 Device Boot Configuration Status869.4 3.3 V I/O Power-Down Control879.5 Peripheral Status and Control879.5.1 Timer Control879.5.2 VPSS Clock and DAC Control879.5.3 DDR2 VTP Control879.5.4 HPI Control879.6 Bandwidth Management889.6.1 Bus Master DMA Priority Control889.6.2 EDMA Transfer Controller Configuration899.7 Boot Control8910 Reset9110.1 Overview9210.2 Reset Pins9210.3 Device Configurations at Reset9210.4 DSP Reset9310.4.1 DSP Local Reset9310.4.2 DSP Module Reset9310.4.2.1 Software Reset Disable (SwRstDisable)9310.4.2.2 Synchronous Reset (SyncReset)9411 Boot Modes95A Revision History97Größe: 596 KBSeiten: 98Language: EnglishHandbuch öffnen