Manuali utente per Texas Instruments TMS320DM643x

Sommario

• Table of Contents

  3
• Preface

  9
• 1 Introduction

  11
  • 1.1 Introduction

    12
  • 1.2 Block Diagram

    12
  • 1.3 DSP Subsystem in TMS320DM643x DMP

    13
    • 1.3.1 Components of the DSP Subsystem

      13
• 2 TMS320C64x+ Megamodule

  15
  • 2.1 Introduction

    16
  • 2.2 TMS320C64x+ CPU

    16
  • 2.3 Memory Controllers

    18
    • 2.3.1 L1P Controller

      18
    • 2.3.2 L1D Controller

      20
    • 2.3.3 L2 Controller

      20
    • 2.3.4 External Memory Controller (EMC)

      21
    • 2.3.5 Internal DMA (IDMA)

      21
  • 2.4 Internal Peripherals

    22
    • 2.4.1 Interrupt Controller (INTC)

      22
    • 2.4.2 Power-Down Controller (PDC)

      22
    • 2.4.3 Bandwidth Manager

      23
• 3 System Memory

  25
  • 3.1 Memory Map

    26
    • 3.1.1 DSP Internal Memory (L1P, L1D, L2)

      26
    • 3.1.2 External Memory

      26
    • 3.1.3 Internal Peripherals

      26
    • 3.1.4 Device Peripherals

      26
  • 3.2 Memory Interfaces Overview

    27
    • 3.2.1 DDR2 External Memory Interface

      27
    • 3.2.2 External Memory Interface

      27
      • 3.2.2.1 Asynchronous EMIF Interface

        27
      • 3.2.2.2 NAND Interface

        27
• 4 Device Clocking

  29
  • 4.1 Overview

    30
  • 4.2  Clock Domains

    30
    • 4.2.1 Core Domains

      30
    • 4.2.2 Core Frequency Flexibility

      32
    • 4.2.3 DDR2/EMIF Clock

      33
    • 4.2.4 I/O Domains

      34
    • 4.2.5 Video Processing Back End

      35
• 5 PLL Controller

  37
  • 5.1 PLL Module

    38
  • 5.2  PLL1 Control

    38
    • 5.2.1 Device Clock Generation

      39
    • 5.2.2 Steps for Changing PLL1/Core Domain Frequency

      39
      • 5.2.2.1 Initialization to PLL Mode from PLL Power Down

        40
      • 5.2.2.2 Changing PLL Multiplier

        41
      • 5.2.2.3 Changing SYSCLK Dividers

        42
  • 5.3 PLL2 Control

    43
    • 5.3.1 Device Clock Generation

      43
    • 5.3.2 Steps for Changing PLL2 Frequency

      44
      • 5.3.2.1 DDR2 Considerations When Modifying PLL2 Frequency

        44
        • 5.3.2.1.1 PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset

          44
        • 5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset

          44
      • 5.3.2.2 Initialization to PLL Mode from PLL Power Down

        45
      • 5.3.2.3 Changing PLL Multiplier

        46
      • 5.3.2.4 Changing SYSCLK Dividers

        47
  • 5.4 PLL Controller Registers

    48
    • 5.4.1 Peripheral ID Register (PID)

      49
    • 5.4.2 Reset Type Status Register (RSTYPE)

      49
    • 5.4.3 PLL Control Register (PLLCTL)

      50
    • 5.4.4 PLL Multiplier Control Register (PLLM)

      51
    • 5.4.5 PLL Controller Divider 1 Register (PLLDIV1)

      51
    • 5.4.6 PLL Controller Divider 2 Register (PLLDIV2)

      52
    • 5.4.7 PLL Controller Divider 3 Register (PLLDIV3)

      52
    • 5.4.8 Oscillator Divider 1 Register (OSCDIV1)

      53
    • 5.4.9 Bypass Divider Register (BPDIV)

      54
    • 5.4.10 PLL Controller Command Register (PLLCMD)

      55
    • 5.4.11 PLL Controller Status Register (PLLSTAT)

      55
    • 5.4.12 PLL Controller Clock Align Control Register (ALNCTL)

      56
    • 5.4.13 PLLDIV Ratio Change Status Register (DCHANGE)

      57
    • 5.4.14 Clock Enable Control Register (CKEN)

      58
    • 5.4.15 Clock Status Register (CKSTAT)

      59
    • 5.4.16 SYSCLK Status Register (SYSTAT)

      60
• 6 Power and Sleep Controller

  61
  • 6.1 Introduction

    62
  • 6.2 Power Domain and Module Topology

    63
  • 6.3 Power Domain and Module States

    64
    • 6.3.1 Power Domain States

      64
    • 6.3.2 Module States

      64
    • 6.3.3 Local Reset

      65
  • 6.4 Executing State Transitions

    65
    • 6.4.1 Power Domain State Transitions

      65
    • 6.4.2 Module State Transitions

      65
  • 6.5 IcePick Emulation Support in the PSC

    66
  • 6.6 PSC Interrupts

    66
    • 6.6.1 Interrupt Events

      66
      • 6.6.1.1 Module State Emulation Events

        67
      • 6.6.1.2 Local Reset Emulation Events

        67
    • 6.6.2 Interrupt Registers

      67
    • 6.6.3 Interrupt Handling

      68
  • 6.7 PSC Registers

    68
    • 6.7.1 Peripheral Revision and Class Information Register (PID)

      69
    • 6.7.2 Interrupt Evaluation Register (INTEVAL)

      69
    • 6.7.3 Module Error Pending Register 1 (MERRPR1)

      70
    • 6.7.4 Module Error Clear Register 1 (MERRCR1)

      70
    • 6.7.5 Power Domain Transition Command Register (PTCMD)

      71
    • 6.7.6 Power Domain Transition Status Register (PTSTAT)

      71
    • 6.7.7 Power Domain Status 0 Register (PDSTAT0)

      72
    • 6.7.8 Power Domain Control 0 Register (PDCTL0)

      73
    • 6.7.9 Module Status n Register (MDSTATn)

      74
    • 6.7.10 Module Control n Register (MDCTLn)

      75
• 7 Power Management

  77
  • 7.1 Overview

    78
  • 7.2 PSC and PLLC Overview

    78
  • 7.3 Clock Management

    79
    • 7.3.1 Module Clock ON/OFF

      79
    • 7.3.2 Module Clock Frequency Scaling

      79
    • 7.3.3 PLL Bypass and Power Down

      79
  • 7.4 DSP Sleep Mode Management

    80
    • 7.4.1 DSP Sleep Modes

      80
    • 7.4.2 DSP Module Clock ON/OFF

      80
      • 7.4.2.1 DSP Module Clock ON

        80
      • 7.4.2.2 DSP Module Clock Off

        81
  • 7.5 3.3 V I/O Power Down

    81
  • 7.6 Video DAC Power Down

    81
• 8 Interrupt Controller

  83
• 9 System Module

  85
  • 9.1 Overview

    86
  • 9.2 Device Identification

    86
  • 9.3 Device Configuration

    86
    • 9.3.1 Pin Multiplexing Control

      86
    • 9.3.2 Device Boot Configuration Status

      86
  • 9.4 3.3 V I/O Power-Down Control

    87
  • 9.5 Peripheral Status and Control

    87
    • 9.5.1 Timer Control

      87
    • 9.5.2 VPSS Clock and DAC Control

      87
    • 9.5.3 DDR2 VTP Control

      87
    • 9.5.4 HPI Control

      87
  • 9.6 Bandwidth Management

    88
    • 9.6.1 Bus Master DMA Priority Control

      88
    • 9.6.2 EDMA Transfer Controller Configuration

      89
  • 9.7 Boot Control

    89
• 10 Reset

  91
  • 10.1 Overview

    92
  • 10.2 Reset Pins

    92
  • 10.3 Device Configurations at Reset

    92
  • 10.4 DSP Reset

    93
    • 10.4.1 DSP Local Reset

      93
    • 10.4.2 DSP Module Reset

      93
      • 10.4.2.1 Software Reset Disable (SwRstDisable)

        93
      • 10.4.2.2 Synchronous Reset (SyncReset)

        94
• 11 Boot Modes

  95
• A Revision History

  97