Intel 82801EB User Manual

Intel

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AC ’97 Programmer’s Reference Manual 3

Contents

Introduction.......................................................................................................................... 7

About This Document ............................................................................................. 7

Reference Documents and Information Sources ................................................... 9

Overview ........................................................................................................................... 11

ICH5 AC ’97 Controller Compatibility .......................................................... 11

Third AC ’97 Component Specification Revision 2.1, Revision 2.2 and
Revision 2.3 Compliant Codecs............................................................ 14

Dedicated S/P DIF DMA Output Channel ............................................. 15

20 Bits Surround PCM Output............................................................... 15

Memory Map Status and Control Registers .......................................... 15

Second Independent Input DMA Engines ............................................. 16

PCI Local Bus Specification, Revision 2.3 Power Management........... 16

General Requirements ......................................................................................... 16

ICH5 AC ’97 Controller Theory of Operation ........................................................... 17

ICH5 AC ’97 Initialization............................................................................. 17

System Reset........................................................................................ 17

Codec Topology.................................................................................... 17

BIOS PCI Configuration ........................................................................ 18

Hardware Interrupt Routing................................................................... 19

PCI Lock ............................................................................................... 19

DMA Engines........................................................................................................ 20

Buffer Descriptor List ............................................................................ 20

DMA Initialization................................................................................... 21

DMA Steady State Operation................................................................ 23

Stopping Transfers................................................................................ 24

FIFO Error Conditions........................................................................... 24

FIFO Underrun .................................................................... 24

FIFO Overrun ...................................................................... 24

Channel Arbitration ............................................................................................... 25

Data Buffers.......................................................................................................... 25

Memory Organization of Data ............................................................... 25

PCM Buffer Restrictions........................................................................ 25

FIFO Organization................................................................................. 26

Multiple Codec/Driver Support.............................................................................. 27

Codec Register Shadowing................................................................... 28

Codec Access Synchronization............................................................. 29

Data Request Synchronization in Audio Split Configurations................ 29

Power Management ............................................................................................. 30

Codec Topologies ................................................................................. 30

Tertiary Codec Topologies................................................... 31

Power Management Transition Maps ................................................... 31

Power Management Topology Considerations ..................................... 34