Panasonic MN101C77C User Manual

Chapter 9    Watchdog Timer

IX - 4

Operation

The watchdog timer counts system clock (fs) as a clock source. If the watchdog timer is overflowes, the

watchdog interrupt (WDIRQ) is generated as an non maskable interrupt (NMI). At reset, the watchdog

timer is stopped, but once the operation is enabled, it cannot be stopped except at reset. The watchdog

timer control register (WDCTR) sets when the watchdog timer is released or how long the time-out

period should be.

This watchdog timer can detect such that the watchdog timer clear is repeated in short cycle. If the

watchdog timer clear is repeated in shorter cycle than the set time (the lowest value of watchdog timer

clear possible), it is regarded as an error and the watchdog interrupt (WDIRQ) is generated.

If the watchdog interrupt (WDIRQ) is generated twice consecutively, it is regarded to be an indication that

the software cannot execute in the intended sequence; thus, a system reset is initiated by the hardware.

The watchdog timer cannot stop, once it starts operation.

(1)

the watchdog timer overflows.

(2)

the watchdog timer clear happens in the shorter cycle than the watchdog timer clear

possible lowest value, set in the watchdog timer control register (WDCTR).

When the watchdog timer detects any error, the watchdog interrupt (WDIRQ) is generated as a non

maskable interrupt (NMI).

Programming of the watchdog timer is generally done in the last step of its programming.

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Usage of Watchdog Timer

When the watchdog timer is used, constant clear in program is needed to prevent an overflow of the

watchdog timer. As a result of the software failure, the software cannot execute in the intended se-

quence, thus the watchdog timer overflows and error is detected.

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How to Detect Incorrect Code Execution

The watchdog timer is executed to be cleared in the certain cycle on the correct code execution. On this

LSI, the watchdog timer detects errors when,