Panasonic MN101C77C User Manual

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Chapter 2  CPU Basics

Reset

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Sequence at Reset

(1)

When reset pin comes to high level from low level, the innternal 14-bit counter (It can be used  as

watchdog timer, too.) starts its operation by system clock. The period from starting its count from

its overflow is called oscillation stabilization wait time.

(2)

During reset, internal register and special function register are initiated.

(3)

After oscillation stabilization wait time, internal reset is released and program is started

from the address  written at address X '4000' at interrupt rector table.

Oscillation stabilization 
wait time

OSC2/XO

VDD

NRST

internal RST