Intel N450 AU80610004653AA User Manual

Datasheet

11

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Processor Core:

— Full support of ACPI C-states as implemented by the following processor C-

states: C0/C1(E)/C2(E)/C4(E)

— Enhanced Intel SpeedStep® Technology

•

Thermal Management 1 (TM1) and Thermal Management 2 (TM2)

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System states: S0, S3, S4 and S5

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DMI: L0s and L1 ASPM power management capability

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The processor is a Micro-FCBGA8 type of package at 22mmx22mm package size

BGA

Ball Grid Array

BLT

Block Level Transfer

CRT

Cathode Ray Tube

DDR2

Second generation Double Data Rate SDRAM memory technology

DMA

Direct Memory Access

DMI

Direct Media Interface

DTS

Digital Thermal Sensor

ECC

Error Correction Code

Enhanced Intel 
SpeedStep

®

 

Technology

Technology that provides power management capabilities to laptops.

Execute Disable Bit

The Execute Disable bit allows memory to be marked as executable or 
non-executable, when combined with a supporting operating system. 
If code attempts to run in non-executable memory the processor 
raises an error to the operating system. This feature can prevent some 
classes of viruses or worms that exploit buffer overrun vulnerabilities 
and can thus help improve the overall security of the system. See the 
Intel

 64 and IA-32 Architectures Software Developer's Manuals for 

more detailed information.

Micro-FBGA

Micro Flip Chip Ball Grid Array

(G)MCH

Legacy component - Graphics Memory Controller Hub.

GPU

Graphics Processing Unit