Intel N450 AU80610004653AA User Manual

18

Datasheet

DDR_A_CK_[1:0]

SDRAM Differential Clock: SDRAM 
Differential clock signal pair.

O

SSTL-1.8

DDR_A_CK#_[1:0]

SDRAM Inverted Differential Clock: 
SDRAM Differential clock signal-pair 
complement.

O

SSTL-1.8

DDR_A_CK_[4:3]

SDRAM Differential Clock: SDRAM 
Differential clock signal pair.

O

SSTL-1.8

DDR_A_CK#_[4:3]

SDRAM Inverted Differential Clock: 
SDRAM Differential clock signal-pair 
complement.

O

SSTL-1.8

DDR_A_CS#_[3:0]

Chip Select: (1 per Rank) used to select 
particular SDRAM components during the 
active state.
There is one Chip Select for each SDRAM rank.

O

SSTL-1.8

DDR_A_CKE_[3:0]

Clock Enable: (1 per Rank) used to:

• Initialize the SDRAM during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-

refresh during STR

O

SSTL-1.8

DDR_A_MA_[14:0]

Multiplexed Address: These signals are used 
to provide the multiplexed row and column 
address to the SDRAM.

O

SSTL-1.8

DDR_A_BS_[2:0]

Bank Select: These signals define which 
banks are selected within each SDRAM rank.

O

SSTL-1.8

DDR_A_RAS#

RAS Control Signal: Used with DDR_A_CAS# 
and DDR_A_WE#
(along with DDR_A_CS#) to define the SDRAM 
commands.

O

SSTL-1.8

DDR_A_CAS#

CAS Control Signal: Used with DDR_A_RAS# 
and DDR_A_WE#
(along with DDR_A_CS#) to define the SDRAM 
commands.

O

SSTL-1.8

DDR_A_WE#

Write Enable Control Signal: Used with 
DDR_A_RAS# and DDR_A_CAS# (along with 
DDR_A_CS#) to define the SDRAM 
commands.

O

SSTL-1.8

DDR_A_DQ_[63:0]

Data Bus: Channel data signal interface to the 
SDRAM data bus

I/O

SSTL-1.8