Intel N450 AU80610004653AA User Manual

Datasheet

19

DDR_A_DM_[7:0]

Data Mask: These signals are used to mask 
individual bytes of data in the case of a partial 
write, and to interrupt burst writes.
When activated during writes, the 
corresponding data groups in the SDRAM are 
masked. There is one DDR_A_DM_[7:0] for 
every data byte lane.

O

SSTL-1.8 

DDR_A_DQS_[7:0]

Data Strobes: DDR_A_DQS_[7:0] and its 
complement signal group make up a 
differential strobe pair. The data is captured at 
the crossing point of DDR_A_DQS_[7:0] and 
its DDR_A_DQS#_[7:0] during read and write 
transactions.

I/O

SSTL-1.8 

DDR_A_DQS#_[7:0]

Data Strobe Complements: These are the 
complementary strobe signals.

I/O

SSTL-1.8 

DDR_A_ODT_[3:0]

On-Die-Termination: Active Termination 
Control

O

SSTL-1.8 

DDR_RPD

System Memory RCOMP signal.

I/O

Analog

DDR_RPU

System Memory RCOMP signal.

I/O

Analog

DDR_VREF

SDRAM Reference Voltage

I

Analog

RSTIN#

Reset In: When asserted, this signal will 
asynchronously reset the CPU logic. The signal is 
connected to the PLTRST# output of the south 
bridge.
This input should have a Schmitt trigger to avoid 
spurious resets. 
This signal is required to be 3.3-V tolerant.

I

HVCMOS

PWROK

Power OK: When asserted, PWROK is an 
indication to the processor that core power has 
been stable.
This input should have a Schmitt trigger to avoid 
spurious resets. This signal is required to be 3.3-
V tolerant.

I

HVCMOS