Intel N450 AU80610004653AA User Manual
Product codes
AU80610004653AA
Power Management
54
Datasheet
5.2
Processor Core Power Management
While executing code, Enhanced Intel
®
SpeedStep Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.
5.2.1
Enhanced Intel® SpeedStep Technology
The following are the key features of Enhanced Intel
®
SpeedStep Technology:
•
Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
efficiency. These operating points are known as P-states.
•
Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency:
voltage is optimized based on the selected frequency:
— If the target frequency is higher than the current frequency, V
CC
is ramped up in
steps to an optimized voltage. This voltage is signaled by the VID pins to the
voltage regulator. Once the voltage is established, the PLL locks on to the target
frequency.
voltage regulator. Once the voltage is established, the PLL locks on to the target
frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the VID pins.
voltage on the VID pins.
G1
S4
Power off
Power off
Off except RTC
Suspend to Disk
G2
S5
Power off
Power off
Off except RTC
Soft Off
G3
NA
Power Off
Power off
Power off
Hard Off
Table 5-41.D, S and C state Combinations
Graphics Adapter
(D) State
Sleep (S)
State
Package (C)
State
Description
D0
S0
C0
Full On, Displaying
D0
S0
C1
Auto-Halt, Displaying
D0
S0
C2/C4
Stop Grant/Deeper Sleep, Displaying
D3
S0
Any
Not Displaying
D3
S3
---
Not Displaying, host core power off.
D3
S4
---
Not Displaying Suspend to disk Host
core power off
core power off
Table 5-40.G, S and C State combinations
Global
(G) State
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System Clocks
Description