Intel N450 AU80610004653AA User Manual

Datasheet

55

— Software-requested transitions are accepted at any time. If a previous transition 

is in progress, the new transition is deferred until the previous transition is 
completed.

•

The processor controls voltage ramp rates internally to ensure glitch-free 
transitions.

•

Because there is low transition latency between P-states, a significant number of 
transitions per second are possible.

•

Improved Thermal Monitor mode.

— When the on-die thermal sensor indicates that the die temperature is too high, 

the processor can automatically perform a transition to a lower frequency and 
voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up transition to the previous frequency and voltage point 
occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system level thermal management.

Dynamic Cache Sizing allows the processor to flush and disable a programmable 
number of L2 cache ways upon each Deeper Sleep entry under the following condition:

•

The C0 timer that tracks continuous residency in the Normal package state, has not 
expired. This timer is cleared during the first entry into Deeper Sleep to allow 
consecutive Deeper Sleep entries to shrink the L2 cache as needed.

•

The predefined L2 shrink threshold is triggered.

The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in 
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the 
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2 
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the 
ratio is zero, then the ratio will not be taken into account for Dynamic Cache Sizing 
decisions.

When the processor core is idle, low-power idle states (C-states) are used to save 
power. More power savings actions are taken for numerically higher C-states. However, 
higher C-states have longer exit and entry latencies. Resolution of C-states occur at the 
thread, processor core, and processor core package level. Thread level C-states are 
available if Hyper-Threading Technology is enabled.