Renesas rl78 User Manual

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User’
s Manual
 
 
 
 
 
 
 
 
 
 
 
 
 
RL78/G1A
 
User’s Manual: Hardware
16
16-Bit Single-Chip Microcontrollers 
 
All information contained in these materials, including products and product specifications, 
represents information on the product at the time of publication and is subject to change by 
Renesas Electronics Corp. without notice. Please review the latest information published by 
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. 
website (http://www.renesas.com). 
www.renesas.com
Rev.2.00  Jul 2013

Summary of Contents of user manual for Renesas rl78

  • Page 1: COVERUser’s Manual RL78/G1A 16 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product...
  • Page 2: Notice Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the...
  • Page 3: NOTES FOR CMOS DEVICES NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a...
  • Page 4: How to Use This Manual How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions...
  • Page 5Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over...
  • Page 6Other Documents Document Name Document No. Renesas MPUs & MCUs RL78 Family R01CP0003E Semiconductor Package Mount Manual Note Quality Grades...
  • Page 7: CONTENTS CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Features ....................................................................................................................................... 1 1.2 List of Part Numbers ................................................................................................................... 4 1.3 Pin Configuration...
  • Page 8 3.3 Instruction Address Addressing ............................................................................................. 79 3.3.1 Relative addressing ...................................................................................................................... 79 3.3.2 Immediate addressing................................................................................................................... 79 3.3.3 Table indirect addressing.................................................................................................................
  • Page 9 4.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤ VDD ............................................... 116 4.4.5 Handling different...
  • Page 10 6.2.1 Timer count register mn (TCRmn) .............................................................................................. 193 6.2.2 Timer data register mn (TDRmn) ................................................................................................ 195 6.3 Registers Controlling...
  • Page 11 6.10.1 Cautions when using timer output............................................................................................... 291 CHAPTER 7 REAL-TIME CLOCK........................................................................................................ 292 7.1 Functions of Real-time Clock................................................................................................. 292 7.2...
  • Page 12 9.2 Configuration of Clock Output/Buzzer Output Controller................................................... 329 9.3 Registers Controlling Clock Output/Buzzer Output Controller .......................................... 329 9.3.1 Clock...
  • Page 13 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) ..................................... 381 11.6.11 Hardware trigger wait mode (scan mode,...
  • Page 14 12.5.2 Master reception ......................................................................................................................... 447 12.5.3 Master transmission/reception .................................................................................................... 457 12.5.4 Slave transmission...................................................................................................................... 467 12.5.5 Slave reception ........................................................................................................................... 477...
  • Page 15 13.5.3 Transfer direction specification ................................................................................................... 591 13.5.4 Acknowledge (ACK).................................................................................................................... 592 13.5.5 Stop condition ............................................................................................................................. 593 13.5.6 Wait ............................................................................................................................................ 594...
  • Page 16 15.5.1 CSI consecutive transmission..................................................................................................... 677 15.5.2 Consecutive capturing of A/D conversion results........................................................................ 679 15.5.3 UART consecutive reception + ACK...
  • Page 17CHAPTER 19 RESET FUNCTION........................................................................................................ 740 19.1 Timing of Reset Operation ..................................................................................................... 742 19.2 States of Operation During Reset Periods ..............................................................................
  • Page 18 24.3 Format of On-chip Debug Option Byte ................................................................................. 798 24.4 Setting of Option Byte ............................................................................................................ 799 CHAPTER 25 FLASH...
  • Page 19 28.1 Conventions Used in Operation List ..................................................................................... 830 28.1.1 Operand identifiers and specification methods ........................................................................... 830 28.1.2 Description of...
  • Page 20 30.6.2 Temperature sensor, internal reference voltage output characteristics ...................................... 948 30.6.3 POR circuit characteristics.......................................................................................................... 948 30.6.4 LVD circuit characteristics..............................................................................................................
  • Page 21: CHAPTER 1 OUTLINE RL78/G1A R01UH0305EJ0200 Rev.2.00 RENESAS MCU Jul 04, 2013 CHAPTER 1 OUTLINE <R> 1.1 Features Ultra-low power consumption technology •...
  • Page 22RL78/G1A CHAPTER 1 OUTLINE DMA (Direct Memory Access) controller • 2 channels • Number of clocks during transfer between 8/16-bit...
  • Page 23RL78/G1A CHAPTER 1 OUTLINE { ROM, RAM capacities Flash ROM Data flash RAM RL78/G1A 25 pins 32 pins 48 pins...
  • Page 24RL78/G1A CHAPTER 1 OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G1A Part...
  • Page 25 RL78/G1A CHAPTER 1 OUTLINE Table 1-1. List of Ordering Part Numbers <R> Pin count Package Note 1 Fields of...
  • Page 26RL78/G1A CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 25-pin products • 25-pin plastic WFLGA (3 × 3 mm,...
  • Page 27 RL78/G1A CHAPTER 1 OUTLINE 1.3.2 32-pin products • 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)...
  • Page 28RL78/G1A CHAPTER 1 OUTLINE 1.3.3 48-pin products • 48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch) P03/ANI16/RxD1/TO00/(KR1) P02/ANI17/TxD1/TI00/(KR0)...
  • Page 29RL78/G1A CHAPTER 1 OUTLINE • 48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch) P03/ANI16/RxD1/TO00/(KR1) P02/ANI17/TxD1/TI00/(KR0) P140/PCLBUZ0/INTP6 P21/ANI1/AVREFM P20/ANI0/AVREFP...
  • Page 30RL78/G1A CHAPTER 1 OUTLINE 1.3.4 64-pin products • 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)...
  • Page 31RL78/G1A CHAPTER 1 OUTLINE • 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch) Top View Bottom View 8...
  • Page 32RL78/G1A CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI12, PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer ANI16 to ANI30: Analog input...
  • Page 33RL78/G1A CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 25-pin products TIMER ARRAY PORT 0 2 P02, P03 UNIT (8ch) TI00/P02...
  • Page 34 RL78/G1A CHAPTER 1 OUTLINE <R> 1.5.2 32-pin products TIMER ARRAY PORT 0 2 P02, P03 UNIT (8ch) TI00/P02 ch0...
  • Page 35 RL78/G1A CHAPTER 1 OUTLINE <R> 1.5.3 48-pin products TIMER ARRAY PORT 0 2 P02, P03 UNIT (8ch) TI00/P02 ch0...
  • Page 36RL78/G1A CHAPTER 1 OUTLINE 1.5.4 64-pin products TIMER ARRAY PORT 0 7 P00 to P06 UNIT (8ch) TI00/P00 ch0 TO00/P01...
  • Page 37 RL78/G1A CHAPTER 1 OUTLINE 1.6 Outline of Functions (1/2) Item 25-pin 32-pin 48-pin 64-pin R5F10E8x R5F10EBx R5F10EGx R5F10ELx Code...
  • Page 38RL78/G1A CHAPTER 1 OUTLINE (2/2) Item 25-pin 32-pin 48-pin 64-pin R5F10E8x R5F10EBx R5F10EGx R5F10ELx Clock output/buzzer output 1 2 2...
  • Page 39: CHAPTER 2 PIN FUNCTIONSRL78/G1A CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Function Pin I/O buffer power supplies depend on the...
  • Page 40 RL78/G1A CHAPTER 2 PIN FUNCTIONS Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions....
  • Page 41 RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) <R> Function Pin I/O After Reset Alternate Function Function Name Type P121 2-2-1...
  • Page 42 RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.1.2 32-pin products (1/2) <R> Function Pin I/O After Reset Alternate Function Function Name...
  • Page 43 RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) <R> Function Pin Type I/O After Reset Alternate Function Function Name P50 7-3-2...
  • Page 44 RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.1.3 48-pin products (1/2) <R> Function Pin I/O After Reset Alternate Function Function Name...
  • Page 45 RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) <R> Function Pin I/O After Reset Alternate Function Function Name Type P40 7-1-1...
  • Page 46 RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.1.4 64-pin products (1/3) <R> Function Pin I/O After Reset Alternate Function Function Name...
  • Page 47 RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/3) <R> Function Pin Type I/O After Reset Alternate Function Function Name P40 7-1-1...
  • Page 48 RL78/G1A CHAPTER 2 PIN FUNCTIONS (3/3) <R> Function Pin Type I/O After Reset Alternate Function Function Name P150 4-3-1...
  • Page 49RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.2 Functions Other than Port Pins 2.2.1 With functions for each product (1/4) Function 64-pin...
  • Page 50RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/4) Function 64-pin 48-pin 32-pin 25-pin Name KR0 √ √ √ (√) KR1 √ √...
  • Page 51RL78/G1A CHAPTER 2 PIN FUNCTIONS (3/4) Function 64-pin 48-pin 32-pin 25-pin Name SI00 √ √ √ √ SI01 √ √...
  • Page 52RL78/G1A CHAPTER 2 PIN FUNCTIONS (4/4) Function 64-pin 48-pin 32-pin 25-pin Name VDD √ √ √ √ EVDD0 √ −...
  • Page 53 RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.2.2 Explanation of function (1/2) Function Name I/O Function ANI0 to ANI12, ANI16 to...
  • Page 54RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Name I/O Function VDD − <25-pin, 32-pin 48-pin> Positive power supply for port...
  • Page 55 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows...
  • Page 56 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> 2.4 Block Diagrams of Pins Figures 2-1 to 2-13 show the block diagrams...
  • Page 57 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-4. Pin Block Diagram for Pin Type 2-2-1 Clock generator CMC OSCSEL/...
  • Page 58 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-5. Pin Block Diagram for Pin Type 4-3-1 WRADPC 0: Analog input...
  • Page 59 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-6. Pin Block Diagram for Pin Type 7-1-1 WRPU EVDD PU register...
  • Page 60 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-7. Pin Block Diagram for Pin Type 7-1-2 WRPU EVDD PU register...
  • Page 61 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-8. Pin Block Diagram for Pin Type 7-3-1 WRPU EVDD PU register...
  • Page 62 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-9. Pin Block Diagram for Pin Type 7-3-2 WRPU EVDD PU register...
  • Page 63 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-10. Pin Block Diagram for Pin Type 8-1-1 WRPU EVDD PU register...
  • Page 64 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-11. Pin Block Diagram for Pin Type 8-1-2 WRPU EVDD PU register...
  • Page 65 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-12. Pin Block Diagram for Pin Type 8-3-2 WRPU EVDD PU register...
  • Page 66 RL78/G1A CHAPTER 2 PIN FUNCTIONS <R> Figure 2-13. Pin Block Diagram for Pin Type 12-1-1 Alternate function RD 1...
  • Page 67: CHAPTER 3 CPU ARCHITECTURERL78/G1A CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/G1A can access a 1...
  • Page 68RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F10ExA (x = 8, B, G)) FFFFFH 03FFFH Special function register...
  • Page 69RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R5F10ExC (x = 8, B, G, L)) FFFFFH 07FFFH Special function...
  • Page 70RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R5F10ExD (x = 8, B, G, L)) FFFFFH 0BFFFH Special function...
  • Page 71RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (R5F10ExE (x = 8, B, G, L)) FFFFFH 0FFFFH Special function...
  • Page 72RL78/G1A CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the...
  • Page 73RL78/G1A CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below....
  • Page 74RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table...
  • Page 75RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (1/2) 64-pin 48-pin 32-pin 25-pin Vector Table Address Interrupt Source 0000H...
  • Page 76RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (2/2) 64-pin 48-pin 32-pin 25-pin Vector Table Address Interrupt Source 0042H...
  • Page 77 RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area <R> The RL78/G1A mirrors the code flash area of 00000H to...
  • Page 78RL78/G1A CHAPTER 3 CPU ARCHITECTURE • Processor mode control register (PMC) This register sets the flash memory space for mirroring...
  • Page 79RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/G1A products incorporate the following RAMs. Table 3-4. Internal...
  • Page 80RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated...
  • Page 81 RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of...
  • Page 82RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/G1A products incorporate the following processor registers. 3.2.1 Control registers The...
  • Page 83 RL78/G1A CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit...
  • Page 84RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the...
  • Page 85 RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to...
  • Page 86RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function....
  • Page 87RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit...
  • Page 88RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit...
  • Page 89RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit...
  • Page 90 RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable...
  • Page 91RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (5/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit...
  • Page 92RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs) Unlike a general-purpose register, each extended SFR (2nd...
  • Page 93RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (1/6) Address Special Function Register (SFR) Name Symbol...
  • Page 94 RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/6) Address Special Function Register (SFR) Name...
  • Page 95RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/6) Address Special Function Register (SFR) Name Symbol...
  • Page 96 RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/6) Address Special Function Register (SFR) Name...
  • Page 97RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/6) Address Special Function Register (SFR) Name Symbol...
  • Page 98RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (6/6) Address Special Function Register (SFR) Name Symbol...
  • Page 99RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter...
  • Page 100RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT...
  • Page 101RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the...
  • Page 102RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such...
  • Page 103RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an...
  • Page 104RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit...
  • Page 105RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data...
  • Page 106RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the...
  • Page 107RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with...
  • Page 108RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-27. Example of [HL + byte], [DE + byte] [HL + byte], [DE +...
  • Page 109RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Example of word[BC] word [BC] FFFFFH <1> <2> Target memory Array of Instruction...
  • Page 110RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-31. Example of ES:word[B], ES:word[C] ES: word [B]㧘ES: word [C] <1> <2> <3> <1>...
  • Page 111RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair...
  • Page 112RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP)...
  • Page 113RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-36. Example of POP POP rp <1> <2> <1> SP+2 SP Stack Instruction code...
  • Page 114RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-38. Example of RET RET <1> SP+4 <1> SP Instruction code SP+3 (SP+3) SP+2...
  • Page 115RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-40. Example of RETI, RETB RETI㧘RETB <1> PSW SP+4 <1> SP Instruction code SP+3...
  • Page 116: CHAPTER 4 PORT FUNCTIONSRL78/G1A CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/G1A microcontrollers are provided with digital I/O...
  • Page 117 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-1. Port Configuration Item Configuration...
  • Page 118 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port...
  • Page 119 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port...
  • Page 120 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an I/O port with an output latch. Port...
  • Page 121 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an I/O port with an output latch. Port...
  • Page 122 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is an I/O port with an output latch. Port...
  • Page 123RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. • Port...
  • Page 124RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-4. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each...
  • Page 125 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the...
  • Page 126 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port....
  • Page 127 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors...
  • Page 128 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.4 Port input mode registers (PIMxx) These registers set the input buffer in 1-bit...
  • Page 129 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.5 Port output mode registers (POMxx) These registers set the output mode in 1-bit...
  • Page 130 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.6 Port mode control registers (PMCxx) These registers set the digital I/O/analog input in...
  • Page 131 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.7 A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7, and...
  • Page 132 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.8 Peripheral I/O redirection register (PIOR) This register is used to specify whether to...
  • Page 133 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.9 Global digital input disable register (GDIDIS) <R> This register is used to prevent...
  • Page 134 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.10 Global analog input disable register (GAIDIS) <R> This register is used to prevent...
  • Page 135RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode...
  • Page 136 RL78/G1A CHAPTER 4 PORT FUNCTIONS <R> 4.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤...
  • Page 137 RL78/G1A CHAPTER 4 PORT FUNCTIONS <R> (2) Setting procedure when using output ports of UART0 to UART2, CSI00, CSI10,...
  • Page 138 RL78/G1A CHAPTER 4 PORT FUNCTIONS <R> 4.5 Register Settings When Using Alternate Function <R> 4.5.1 Basic concept when using...
  • Page 139 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-5. Concept of Basic Settings Output Settings of Unused Alternate Function Output Function...
  • Page 140 RL78/G1A CHAPTER 4 PORT FUNCTIONS <R> 4.5.3 Register setting examples for used port and alternate functions Register setting examples...
  • Page 141 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (1/17)...
  • Page 142 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (2/17)...
  • Page 143 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (3/17)...
  • Page 144 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (4/17)...
  • Page 145 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (5/17)...
  • Page 146 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (6/17)...
  • Page 147 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (7/17)...
  • Page 148 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (8/17)...
  • Page 149 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (9/17)...
  • Page 150 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (10/17)...
  • Page 151 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (11/17)...
  • Page 152 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (12/17)...
  • Page 153 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (13/17)...
  • Page 154 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (14/17)...
  • Page 155 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (16/17)...
  • Page 156 RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6. Setting Examples of Registers and Output Latches When Using Alternate Function (17/17)...
  • Page 157RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-bit manipulation instruction for port register...
  • Page 158 RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings <R> For an output pin to which...
  • Page 159: CHAPTER 5 CLOCK GENERATORRL78/G1A CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR The presence or absence of connecting resonator pin for main system...
  • Page 160 RL78/G1A CHAPTER 5 CLOCK GENERATOR (2) Subsystem clock • XT1 clock oscillator This circuit oscillates a clock of fXT...
  • Page 161 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1....
  • Page 162 <R> Figure 5-1. Block Diagram of Clock Generator Internal bus RL78/G1A Clock operation mode Jul 04, 2013 Clock operation...
  • Page 163 RL78/G1A CHAPTER 5 CLOCK GENERATOR Remark fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External...
  • Page 164RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H...
  • Page 165 RL78/G1A CHAPTER 5 CLOCK GENERATOR Cautions 7. The XT1 oscillator is a circuit with low amplification in order to...
  • Page 166RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware...
  • Page 167RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations...
  • Page 168RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-2. Stopping Clock Method Clock Condition Before Stopping Clock Setting of CSC (Invalidating External...
  • Page 169 RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After...
  • Page 170 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) <R> This register is used to select...
  • Page 171 RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset:...
  • Page 172RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying...
  • Page 173RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/3) Address: F00F0H After reset: 00H...
  • Page 174RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (3/3) Address: F00F0H After reset: 00H...
  • Page 175 RL78/G1A CHAPTER 5 CLOCK GENERATOR <R> 5.3.7 Subsystem clock supply mode control register (OSMC) This register is used to...
  • Page 176 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip...
  • Page 177RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy...
  • Page 178RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator...
  • Page 179 RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-12. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External...
  • Page 180RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-13 shows examples of incorrect resonator connection. Figure 5-13. Examples of Incorrect Resonator Connection...
  • Page 181RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-13. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f)...
  • Page 182 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G1A. The...
  • Page 183RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation...
  • Page 184RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-14. Clock Generator Operation When Power Supply Voltage Is Turned On Lower limit of...
  • Page 185RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the...
  • Page 186RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock...
  • Page 187 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware...
  • Page 188RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram...
  • Page 189RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers....
  • Page 190 RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock...
  • Page 191 RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock...
  • Page 192 RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (4/5) (9) CPU clock...
  • Page 193 RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (5/5) (11) • STOP...
  • Page 194 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before...
  • Page 195RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-5. Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before...
  • Page 196RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and system clock By setting bits 4...
  • Page 197RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for...
  • Page 198 RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.7 Resonator and Oscillator Constants The resonators for which the operation is verified and...
  • Page 199RL78/G1A CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: As of February, 2013 (1/3) Note 1 Manufacturer Resonator Part Number SMD/...
  • Page 200RL78/G1A CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: As of February, 2013 (2/3) Note 1 Manufacturer Resonator Part Number SMD/...
  • Page 201 RL78/G1A CHAPTER 5 CLOCK GENERATOR <R> (1) X1 oscillation: As of February, 2013 (3/3) Manufacturer Resonator Part Number SMD/...
  • Page 202: CHAPTER 6 TIMER ARRAY UNITRL78/G1A CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The timer array unit is provided in all products...
  • Page 203RL78/G1A CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a...
  • Page 204RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1...
  • Page 205 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a...
  • Page 206RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using...
  • Page 207RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) Timer array unit is...
  • Page 208 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware....
  • Page 209RL78/G1A CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel...
  • Page 210 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-1. Entire Configuration of Timer Array Unit 0 (Example: 64-pin products)...
  • Page 211 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channel 0, 2, 4, 6 of Timer...
  • Page 212RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Internal Block Diagram of Channel 5 of Timer Array Unit 0 Interrupt...
  • Page 213RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register...
  • Page 214RL78/G1A CHAPTER 6 TIMER ARRAY UNIT The TCRmn register read value differs as follows according to operation mode changes and...
  • Page 215RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a...
  • Page 216RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following...
  • Page 217 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or...
  • Page 218 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) <R> The TPSm register is a...
  • Page 219 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H,...
  • Page 220RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (2/2) Address: F01B6H, F01B7H...
  • Page 221RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of...
  • Page 222RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00)...
  • Page 223RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00)...
  • Page 224RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00)...
  • Page 225RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Mode Register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00)...
  • Page 226RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of...
  • Page 227RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to...
  • Page 228RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register...
  • Page 229RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register...
  • Page 230RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select...
  • Page 231RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output enable register m (TOEm) The TOEm register is used to enable...
  • Page 232RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output register m (TOm) The TOm register is a buffer register of...
  • Page 233RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output level register m (TOLm) The TOLm register is a register that...
  • Page 234RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output mode register m (TOMm) The TOMm register is used to control...
  • Page 235 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Input switch control register (ISC) The ISC1 and ISC0 bits of the...
  • Page 236 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to...
  • Page 237RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-22. Format of Noise Filter Enable Register 1 (NFEN1) Address: F0071H After reset:...
  • Page 238 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT <R> 6.3.15 Registers controlling port functions of pins to be used for timer...
  • Page 239RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation...
  • Page 240RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Example TAU0 CKm0 Channel group 1 Channel 0: Master (Simultaneous channel operation function) Channel...
  • Page 241RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The...
  • Page 242RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (fTCLK) The count clock (fTCLK) of the...
  • Page 243RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn...
  • Page 244RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Operation of timer count register mn (TCRmn) is enabled...
  • Page 245RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1)...
  • Page 246 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds...
  • Page 247 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled...
  • Page 248RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing...
  • Page 249RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled...
  • Page 250RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn Pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-30....
  • Page 251RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn pin output setting The following figure shows the procedure and status transition...
  • Page 252RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on channel output operation (1) Changing values set in the registers TOm,...
  • Page 253RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The...
  • Page 254RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM...
  • Page 255RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a)...
  • Page 256RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-35. Set/Reset Timing Operating Statuses (1) Basic operation timing fTCLK INTTMmn Master Internal...
  • Page 257RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting...
  • Page 258RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Caution While timer output is enabled (TOEmn = 1), even if the output by...
  • Page 259RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.7 Timer Input (TImn) Control 6.7.1 TImn pin input circuit configuration The signal input...
  • Page 260RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input When timer input pins are not used, the operating...
  • Page 261RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8 Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square...
  • Page 262RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-41. Block Diagram of Operation as Interval Timer/Square Wave Output Clock selection CKm1...
  • Page 263RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave...
  • Page 264RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave...
  • Page 265 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation...
  • Page 266RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware...
  • Page 267RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as...
  • Page 268RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as External Event Counter TSmn TEmn...
  • Page 269RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (1/2)...
  • Page 270RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (2/2)...
  • Page 271 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure When External Event Counter Function Is Used Software Operation...
  • Page 272RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as frequency divider (channel 0 of unit 0 only) The timer array...
  • Page 273RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1)...
  • Page 274 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers During Operation as Frequency Divider...
  • Page 275 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware...
  • Page 276 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input pulse interval measurement The count value can be captured...
  • Page 277RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0...
  • Page 278RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Pulse Interval (a)...
  • Page 279 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software...
  • Page 280RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as input signal high-/low-level width measurement Caution When using a channel to...
  • Page 281 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement <R>...
  • Page 282RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width...
  • Page 283 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used...
  • Page 284RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.6 Operation as delay counter It is possible to start counting down when the...
  • Page 285RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn...
  • Page 286RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer...
  • Page 287RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer...
  • Page 288 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware...
  • Page 289RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.9 Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse...
  • Page 290RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count...
  • Page 291RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation as One-Shot Pulse Output Function (Start...
  • Page 292 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers When One-Shot Pulse Output Function...
  • Page 293RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When One-Shot Pulse Output Function Is...
  • Page 294 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware...
  • Page 295 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware...
  • Page 296RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to...
  • Page 297RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Block Diagram of Operation as PWM Function Master channel (interval timer mode)...
  • Page 298RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH...
  • Page 299 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers When PWM Function (Master Channel)...
  • Page 300RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When PWM Function (Slave Channel) Is...
  • Page 301RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status...
  • Page 302 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware...
  • Page 303RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using...
  • Page 304RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Block Diagram of Operation as Multiple PWM Output Function (output two types...
  • Page 305RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Basic Timing of Operation as Multiple PWM Output Function (Output...
  • Page 306RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0,...
  • Page 307 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Set Contents of Registers When Multiple PWM Output Function...
  • Page 308RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Example of Set Contents of Registers When Multiple PWM Output Function (Slave...
  • Page 309RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation...
  • Page 310 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software...
  • Page 311 RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions when using timer output...
  • Page 312: CHAPTER 7 REAL-TIME CLOCK RL78/G1A CHAPTER 7 REAL-TIME CLOCK CHAPTER 7 REAL-TIME CLOCK 7.1 Functions of Real-time Clock The real-time clock has the...
  • Page 313RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.2 Configuration of Real-time Clock The real-time clock includes the following hardware. Table 7-1. Configuration...
  • Page 314 RL78/G1A CHAPTER 7 REAL-TIME CLOCK Figure 7-1. Block Diagram of Real-time Clock Real-time clock control register 1 Real-time clock...
  • Page 315 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers....
  • Page 316 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable...
  • Page 317RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to...
  • Page 318 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.3 Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register...
  • Page 319 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.4 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register...
  • Page 320 RL78/G1A CHAPTER 7 REAL-TIME CLOCK Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) Address: FFF9EH After...
  • Page 321 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.5 Second count register (SEC) The SEC register is an 8-bit register that takes...
  • Page 322 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.7 Hour count register (HOUR) The HOUR register is an 8-bit register that takes...
  • Page 323RL78/G1A CHAPTER 7 REAL-TIME CLOCK Table 7-2 shows the relationship between the setting value of the AMPM bit, the hour...
  • Page 324 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.8 Day count register (DAY) The DAY register is an 8-bit register that takes...
  • Page 325 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.9 Week count register (WEEK) The WEEK register is an 8-bit register that takes...
  • Page 326 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.10 Month count register (MONTH) The MONTH register is an 8-bit register that takes...
  • Page 327RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.12 Watch error correction register (SUBCUD) This register is used to correct the watch with...
  • Page 328RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The...
  • Page 329 RL78/G1A CHAPTER 7 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm Day 12-Hour Display...
  • Page 330RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4 Real-time Clock Operation 7.4.1 Starting operation of real-time clock Figure 7-19. Procedure for Starting...
  • Page 331RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when...
  • Page 332RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first....
  • Page 333RL78/G1A CHAPTER 7 REAL-TIME CLOCK Figure 7-22. Procedure for Writing Real-time Clock Start Stops SEC to YEAR counters. RWAIT =...
  • Page 334RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE...
  • Page 335 RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.5 1 Hz output of real-time clock Figure 7-24. 1 Hz Output Setting Procedure...
  • Page 336RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.6 Example of watch error correction of real-time clock The watch can be corrected with...
  • Page 337 RL78/G1A CHAPTER 7 REAL-TIME CLOCK <R> Correction example 1 Example of correcting from 32772.3 Hz to 32768 Hz (32772.3...
  • Page 338 <R> Figure 7-25. Correction Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0,...
  • Page 339RL78/G1A CHAPTER 7 REAL-TIME CLOCK Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz +...
  • Page 340 <R> Figure 7-26. Correction Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0,...
  • Page 341: CHAPTER 8 12-BIT INTERVAL TIMER RL78/G1A CHAPTER 8 INTERVAL TIMER CHAPTER 8 12-BIT INTERVAL TIMER 8.1 Functions of 12-bit Interval Timer An interrupt (INTIT)...
  • Page 342 RL78/G1A CHAPTER 8 INTERVAL TIMER 8.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the...
  • Page 343RL78/G1A CHAPTER 8 INTERVAL TIMER 8.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to...
  • Page 344RL78/G1A CHAPTER 8 INTERVAL TIMER 8.3.3 Interval timer control register (ITMC) This register is used to set up the starting...
  • Page 345 RL78/G1A CHAPTER 8 INTERVAL TIMER 8.4 12-bit Interval Timer Operation 8.4.1 12-bit interval timer operation timing The count value...
  • Page 346RL78/G1A CHAPTER 8 INTERVAL TIMER 8.4.2 Starting counter operation after returning from HALT or STOP mode and then shifting to...
  • Page 347: CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER The number of output pins of...
  • Page 348RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller Internal bus Clock output...
  • Page 349RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes...
  • Page 350 RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H...
  • Page 351 RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER <R> 9.3.2 Registers controlling port functions of pins to be used for...
  • Page 352 RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.4 Operations of Clock Output/Buzzer Output Controller One pin can be used...
  • Page 353: CHAPTER 10 WATCHDOG TIMER RL78/G1A CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer <R> The counting operation of...
  • Page 354 RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. <R> Table...
  • Page 355RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable...
  • Page 356 RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the...
  • Page 357 RL78/G1A CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT, STOP, and SNOOZE...
  • Page 358RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the...
  • Page 359RL78/G1A CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 29/fIL, the window close time and open...
  • Page 360: CHAPTER 11 A/D CONVERTER RL78/G1A CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER The number of analog input channels of the A/D converter...
  • Page 361 RL78/G1A CHAPTER 11 A/D CONVERTER Various A/D conversion modes can be specified by using the mode combinations below. Trigger...
  • Page 362 Figure 11-1. Block Diagram of A/D Converter Internal bus RL78/G1A Jul 04, 2013 A/D port configuration A/D test register...
  • Page 363RL78/G1A CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to...
  • Page 364RL78/G1A CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap...
  • Page 365RL78/G1A CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter is controlled by the following registers....
  • Page 366 RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable...
  • Page 367 RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for...
  • Page 368RL78/G1A CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation 0 0...
  • Page 369 RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables...
  • Page 370 RL78/G1A CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (1/4) (1) 12-bit resolution mode (ADTYP =...
  • Page 371RL78/G1A CHAPTER 11 A/D CONVERTER Cautions 1. The A/D conversion time must also be within the relevant range of conversion...
  • Page 372 RL78/G1A CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (2/4) (2) 12-bit resolution mode (ADTYP =...
  • Page 373RL78/G1A CHAPTER 11 A/D CONVERTER Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion...
  • Page 374 RL78/G1A CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (3/4) (3) 8-bit resolution mode (ADTYP =...
  • Page 375RL78/G1A CHAPTER 11 A/D CONVERTER Cautions 1. The A/D conversion time must also be within the relevant range of conversion...
  • Page 376 RL78/G1A CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (4/4) (4) 8-bit resolution mode (ADTYP =...
  • Page 377RL78/G1A CHAPTER 11 A/D CONVERTER Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion...
  • Page 378RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS...
  • Page 379 RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the...
  • Page 380RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.4 A/D converter mode register 2 (ADM2) This register is used to select the +...
  • Page 381 RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After...
  • Page 382 RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.5 12-bit A/D conversion result register (ADCR) This register is a 16-bit register that...
  • Page 383RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that indicate...
  • Page 384RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the...
  • Page 385 RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-11. Format of Analog Input Channel Specification Register (ADS) (2/2) Address: FFF31H After...
  • Page 386RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify...
  • Page 387 RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.10 A/D test register (ADTES) <R> This register is used to select the +...
  • Page 388 RL78/G1A CHAPTER 11 A/D CONVERTER <R> 11.3.11 Registers controlling port function of analog input pins Set up the registers...
  • Page 389RL78/G1A CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The...
  • Page 390 RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-15. Conversion Operation of A/D Converter (Software Trigger Mode) ADCS ← 1 or...
  • Page 391RL78/G1A CHAPTER 11 A/D CONVERTER 11.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to...
  • Page 392RL78/G1A CHAPTER 11 A/D CONVERTER 11.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below....
  • Page 393RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the...
  • Page 394RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the...
  • Page 395RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the...
  • Page 396RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status,...
  • Page 397RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status,...
  • Page 398RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status,...
  • Page 399RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status,...
  • Page 400RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status,...
  • Page 401RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status,...
  • Page 402RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status,...
  • Page 403RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status,...
  • Page 404RL78/G1A CHAPTER 11 A/D CONVERTER 11.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is...
  • Page 405 RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.1 Setting up software trigger mode <R> Figure 11-29. Setting up Software Trigger Mode...
  • Page 406 RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.2 Setting up hardware trigger no-wait mode <R> Figure 11-30. Setting up Hardware Trigger...
  • Page 407 RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.3 Setting up hardware trigger wait mode <R> Figure 11-31. Setting up Hardware Trigger...
  • Page 408 RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software...
  • Page 409 RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.5 Setting up test mode <R> Figure 11-33. Setting up Test Mode Start of...
  • Page 410RL78/G1A CHAPTER 11 A/D CONVERTER 11.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a...
  • Page 411RL78/G1A CHAPTER 11 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result...
  • Page 412RL78/G1A CHAPTER 11 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result...
  • Page 413 RL78/G1A CHAPTER 11 A/D CONVERTER <R> Figure 11-37. Flowchart for Setting up SNOOZE Mode Start of setup The ADCEN...
  • Page 414RL78/G1A CHAPTER 11 A/D CONVERTER 11.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D...
  • Page 415RL78/G1A CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog...
  • Page 416 RL78/G1A CHAPTER 11 A/D CONVERTER 11.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP...
  • Page 417RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-44. Analog Input Pin Connection If there is a possibility that noise equal to...
  • Page 418RL78/G1A CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if...
  • Page 419RL78/G1A CHAPTER 11 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below....
  • Page 420: CHAPTER 12 SERIAL ARRAY UNITRL78/G1A CHAPTER 12 SERIAL ARRAY UNIT CHAPTER 12 SERIAL ARRAY UNIT A single serial array unit has up to four...
  • Page 421RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G1A has...
  • Page 422RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0 to UART2) This is a start-stop synchronization function using two lines:...
  • Page 423RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) This is a clocked communication...
  • Page 424RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit The serial array unit includes the following hardware....
  • Page 425 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of the serial array unit 0. Figure...
  • Page 426 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2 shows the block diagram of the serial array unit 1. Figure...
  • Page 427 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.2.1 Shift register This is a 9-bit register that converts parallel data into...
  • Page 428 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-3. Format of Serial Data Register mn (SDRmn) (mn = 00,...
  • Page 429RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following...
  • Page 430 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable...
  • Page 431 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit...
  • Page 432 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that...
  • Page 433 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H...
  • Page 434 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address:...
  • Page 435 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address:...
  • Page 436 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Caution Be sure to clear bits 3, 6, and 11 to “0”. (Also...
  • Page 437 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-8. Format of Serial Data Register mn (SDRmn) Address: FFF10H, FFF11H (SDR00),...
  • Page 438 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a...
  • Page 439 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that...
  • Page 440 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-10. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H...
  • Page 441RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.8 Serial channel start register m (SSm) The SSm register is a trigger register...
  • Page 442RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.9 Serial channel stop register m (STm) The STm register is a trigger register...
  • Page 443RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data...
  • Page 444RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.11 Serial output enable register m (SOEm) The SOEm register is a register that...
  • Page 445 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.12 Serial output register m (SOm) The SOm register is a buffer register...
  • Page 446RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.13 Serial output level register m (SOLm) The SOLm register is a register that...
  • Page 447 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-17. Examples of Reverse Transmit Data (a) Non-reverse Output (SOLmn =...
  • Page 448 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.14 Serial standby control register 0 (SSC0) The SSC0 register is used to...
  • Page 449 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.15 Input switch control register (ISC) The ISC1 and ISC0 bits of the...
  • Page 450 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to...
  • Page 451RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.17 Registers controlling port functions of serial input/output pins Using the serial array unit...
  • Page 452RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation Stop Mode Each serial interface of serial array unit has the operation...
  • Page 453RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the operation by channels The stopping of the operation by channels is...
  • Page 454 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) Communication...
  • Page 455RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) are channels...
  • Page 456RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) performs the following seven types...
  • Page 457 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master transmission <R> Master transmission is that the RL78 microcontroller outputs a...
  • Page 458RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-24. Example of Contents of Registers for Master Transmission of...
  • Page 459RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O...
  • Page 460RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-25. Initial Setting Procedure for Master Transmission Starting initial setting...
  • Page 461 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Procedure for Stopping Master Transmission Starting setting to stop If there...
  • Page 462RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-27. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop...
  • Page 463 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-28. Timing Chart of Master Transmission...
  • Page 464 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication For...
  • Page 465 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-30. Timing Chart of Master...
  • Page 466 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For...
  • Page 467 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master reception <R> Master reception is that the RL78 microcontroller outputs a...
  • Page 468RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-32. Example of Contents of Registers for Master Reception of...
  • Page 469RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O...
  • Page 470RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-33. Initial Setting Procedure for Master Reception Starting initial setting...
  • Page 471 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Procedure for Stopping Master Reception Starting setting to stop If there...
  • Page 472RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-35. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop...
  • Page 473 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-36. Timing Chart of Master Reception...
  • Page 474 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-37. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication For...
  • Page 475 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 12-38. Timing Chart of Master...
  • Page 476 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-39. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication...
  • Page 477 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master transmission/reception <R> Master transmission/reception is that the RL78 microcontroller outputs a...
  • Page 478RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-40. Example of Contents of Registers for Master Transmission/Reception of...
  • Page 479RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O...
  • Page 480RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting...
  • Page 481 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-42. Procedure for Stopping Master Transmission/Reception Starting setting to stop If there...
  • Page 482RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop...
  • Page 483 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-44. Timing Chart of Master Transmission/Reception...
  • Page 484 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-45. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For...
  • Page 485 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-46. Timing Chart of Master...
  • Page 486 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1>...
  • Page 487 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave transmission <R> Slave transmission is that the RL78 microcontroller transmits data...
  • Page 488RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-48. Example of Contents of Registers for Slave Transmission of...
  • Page 489RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O...
  • Page 490RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-49. Initial Setting Procedure for Slave Transmission Starting initial setting...
  • Page 491 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Procedure for Stopping Slave Transmission Starting setting to stop If there...
  • Page 492 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-51. Procedure for Resuming Slave Transmission Starting setting for resumption No Wait...
  • Page 493 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-52. Timing Chart of Slave Transmission...
  • Page 494 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-53. Flowchart of Slave Transmission (in Single-Transmission Mode) <R> Starting CSI communication...
  • Page 495 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-54. Timing Chart of Slave...
  • Page 496 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting <1>...
  • Page 497 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave reception <R> Slave reception is that the RL78 microcontroller receives data...
  • Page 498RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-56. Example of Contents of Registers for Slave Reception of...
  • Page 499RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O...
  • Page 500RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-57. Initial Setting Procedure for Slave Reception Starting initial settings...
  • Page 501 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-58. Procedure for Stopping Slave Reception Starting setting to stop If there...
  • Page 502RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-59. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop...
  • Page 503 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-60. Timing Chart of Slave Reception...
  • Page 504 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For...
  • Page 505 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave transmission/reception <R> Slave transmission/reception is that the RL78 microcontroller transmits/receives data...
  • Page 506RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-62. Example of Contents of Registers for Slave Transmission/Reception of...
  • Page 507RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O...
  • Page 508RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting...
  • Page 509 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there...
  • Page 510RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption No Wait until...
  • Page 511 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-66. Timing Chart of Slave Transmission/Reception...
  • Page 512 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-67. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For...
  • Page 513 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-68. Timing Chart of Slave...
  • Page 514 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1>...
  • Page 515 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 SNOOZE mode function SNOOZE mode makes CSI operate reception by SCKp pin...
  • Page 516 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-71. Flowchart of SNOOZE Mode Operation (Once Startup) SNOOZE mode operation No...
  • Page 517 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 12-72. Timing Chart of SNOOZE Mode...
  • Page 518 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-73. Flowchart of SNOOZE Mode Operation (Continuous Startup) SNOOZE mode operation No...
  • Page 519RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00,...
  • Page 520RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-2. Selection of Operation Clock for 3-Wire Serial I/O Note SMRmn SPSm Register...
  • Page 521RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10,...
  • Page 522 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0 to UART2) Communication This is a start-stop synchronization...
  • Page 523RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. UART1 uses channels 2 and 3...
  • Page 524RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Select any function for each channel. Only the selected function is possible. If UART0...
  • Page 525 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART transmission <R> UART transmission is an operation to transmit data from...
  • Page 526 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-75. Example of Contents of Registers for UART Transmission...
  • Page 527RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-75. Example of Contents of Registers for UART Transmission of UART (UART0 to...
  • Page 528 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-76. Initial Setting Procedure for UART Transmission Starting initial...
  • Page 529 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-77. Procedure for Stopping UART Transmission Starting setting to stop If there...
  • Page 530 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-78. Procedure for Resuming UART Transmission Starting setting for resumption Completing master...
  • Page 531 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-79. Timing Chart of UART Transmission...
  • Page 532 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-80. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For...
  • Page 533 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-81. Timing Chart of UART...
  • Page 534 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-82. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication...
  • Page 535 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART reception <R> UART reception is an operation wherein the RL78 microcontroller...
  • Page 536 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-83. Example of Contents of Registers for UART Reception...
  • Page 537RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-83. Example of Contents of Registers for UART Reception of UART (UART0 to...
  • Page 538 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-84. Initial Setting Procedure for UART Reception Starting initial...
  • Page 539RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-86. Procedure for Resuming UART Reception Starting setting for resumption No Stop the...
  • Page 540 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-87. Timing Chart of UART Reception SSmn STmn SEmn...
  • Page 541 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-88. Flowchart of UART Reception <R> Starting UART communication For the initial...
  • Page 542 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 SNOOZE mode function <R> The SNOOZE mode makes the UART perform reception...
  • Page 543RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. UART Reception Baud Rate Setting in the SNOOZE Mode High-speed On- UART...
  • Page 544 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because EOCm1 =...
  • Page 545 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: error interrupt (INTSRE0)...
  • Page 546 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-91. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1...
  • Page 547 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: error interrupt (INTSRE0)...
  • Page 548 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1)...
  • Page 549 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Caution If the SSECm bit is 1, the PEFm1, FEFm1, and OVFm1 flags...
  • Page 550RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART...
  • Page 551RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-4. Selection of Operation Clock For UART Note SMRmn SPSm Register Operation Clock...
  • Page 552RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0 to...
  • Page 553RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception...
  • Page 554RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication The...
  • Page 555RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.7 LIN Communication Operation 12.7.1 LIN transmission Of UART transmission, UART2 of the 32,...
  • Page 556 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT LIN stands for Local Interconnect Network and is a low-speed (1 to 20...
  • Page 557RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-98. Flowchart for LIN Transmission Starting LIN Operation of the hardware (referenc e)...
  • Page 558RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 LIN reception Of UART reception, UART2 of the 32, 48, and 64-pin products...
  • Page 559RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-99. Reception Operation of LIN Wakeup signal Break field Sync field Identification Data...
  • Page 560RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-100. Flowchart for LIN Reception Starting LIN Status of LIN bus signal and...
  • Page 561RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-101 and figure 12-102 show the configuration of a port that manipulates reception...
  • Page 562RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-102. Port Configuration for Manipulating Reception of LIN (48, 64-pin) Selector P14/RxD2/SI20/SDA20 RXD2...
  • Page 563RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT The peripheral functions used for the LIN communication operation are as follows. <Peripheral functions...
  • Page 564RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 2 12.8 Operation of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication...
  • Page 565 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT The channel supporting simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) is channels...
  • Page 566RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) performs the following four types of...
  • Page 567 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.1 Address field transmission Address field transmission is a transmission operation that first...
  • Page 568 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting 2 Figure 12-103. Example of Contents of Registers for Address...
  • Page 569RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-103. Example of Contents of Registers for Address Field Transmission of Simplified I2C...
  • Page 570RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-104. Initial Setting Procedure for Address Field Transmission Starting initial...
  • Page 571RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-105. Timing Chart of Address Field Transmission SSmn SEmn SOEmn...
  • Page 572RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 2 Figure 12-106. Flowchart of Simplified I C Address Field Transmission Transmitting address field...
  • Page 573 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.2 Data transmission Data transmission is an operation to transmit data to the...
  • Page 574 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-107. Example of Contents of Registers for Data Transmission...
  • Page 575RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-107. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00,...
  • Page 576RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-108. Timing Chart of Data Transmission SSmn “L” SEmn “H”...
  • Page 577 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.3 Data reception Data reception is an operation to receive data to the...
  • Page 578 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-110. Example of Contents of Registers for Data Reception...
  • Page 579RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-110. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00,...
  • Page 580RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-111. Timing Chart of Data Reception (a) When starting data...
  • Page 581RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-112. Flowchart of Data Reception Address field transmission completed Data reception completed Stop...
  • Page 582RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.4 Stop condition generation After all data are transmitted to or received from the...
  • Page 583RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.5 Calculating transfer rate The transfer rate for simplified I2C (IIC00, IIC01, IIC10, IIC11,...
  • Page 584RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-5. Selection of Operation Clock For Simplified I2C Note SMRmn SPSm Register Operation...
  • Page 585 RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10,...
  • Page 586: CHAPTER 13 SERIAL INTERFACE IICARL78/G1A CHAPTER 13 SERIAL INTERFACE IICA CHAPTER 13 SERIAL INTERFACE IICA 13.1 Functions of Serial Interface IICA Serial interface IICA...
  • Page 587RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-1. Block Diagram of Serial Interface IICA Internal bus IICA status register 0...
  • Page 588RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example...
  • Page 589RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table...
  • Page 590RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-4. Format of Slave Address Register 0 (SVA0) Address: F0234H After reset: 00H...
  • Page 591RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (13) Bus status detector This circuit detects whether or not the bus is released...
  • Page 592RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3 Registers Controlling Serial Interface IICA Serial interface IICA0 is controlled by the following...
  • Page 593RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.2 IICA control register 00 (IICCTL00) This register is used to enable/stop I2C operations,...
  • Page 594RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (1/4) Address: F0230H After reset:...
  • Page 595RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (2/4) Note 1 SPIE0 Enable/disable...
  • Page 596 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4) Notes 1, 2...
  • Page 597 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (4/4) Note SPT0 Stop...
  • Page 598RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.3 IICA status register 0 (IICS0) This register indicates the status of I2C. The...
  • Page 599RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension...
  • Page 600RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge...
  • Page 601RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.4 IICA flag register 0 (IICF0) This register sets the operation mode of I2C...
  • Page 602RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-8. Format of IICA Flag Register 0 (IICF0) Address: FFF52H After reset: 00H...
  • Page 603RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.5 IICA control register 01 (IICCTL01) This register is used to set the operation...
  • Page 604 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 Detection of...
  • Page 605 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.6 IICA low-level width setting register 0 (IICWL0) This register is used to...
  • Page 606RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.8 Port mode register 6 (PM6) This register sets the input/output of port 6...
  • Page 607RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.4 I2C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCLA0) and...
  • Page 608RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock...
  • Page 609 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Cautions 1. The fastest operation frequency of the IICA operation clock (fMCK) is...
  • Page 610RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s...
  • Page 611RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.2 Addresses The address is defined by the 7 bits of data that follow...
  • Page 612RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at...
  • Page 613RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0...
  • Page 614RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.6 Wait The wait is used to notify the communication partner that a device...
  • Page 615RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-20. Wait (2/2) (2) When master and slave devices both have a nine-clock...
  • Page 616RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.7 Canceling wait The I2C usually cancels a wait state by the following processing....
  • Page 617RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3...
  • Page 618RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.9 Address match detection method In I2C bus mode, the master device can select...
  • Page 619RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0...
  • Page 620RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Table 13-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt...
  • Page 621 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA <R> 13.5.13 Wakeup function The I2C bus slave function is a function that...
  • Page 622RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-23. Flow When Setting WUP0 = 0 Upon Address Match (Including Extension Code...
  • Page 623 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-24. When Operating as Master Device After Releasing STOP Mode Other than...
  • Page 624RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of...
  • Page 625RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-25 shows the communication reservation timing. Figure 13-25. Communication Reservation Timing Write to...
  • Page 626RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-27. Communication Reservation Protocol DI SET1 STT0 Sets STT0 flag (communication reservation) Define...
  • Page 627RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register...
  • Page 628 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.15 Cautions (1) When STCEN = 0 Immediately after I2C operation is enabled...
  • Page 629RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master...
  • Page 630 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 13-28. Master Operation in Single-Master System...
  • Page 631 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 13-29. Master Operation in Multi-Master System...
  • Page 632 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (2/4) A Enables reserving communication. STT0...
  • Page 633 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (4/4) C Starts communication Writing IICAn...
  • Page 634RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically,...
  • Page 635 RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface...
  • Page 636RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is...
  • Page 637RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop...
  • Page 638RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop...
  • Page 639RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i)...
  • Page 640RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data...
  • Page 641RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop...
  • Page 642RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop...
  • Page 643RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop...
  • Page 644RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in...
  • Page 645RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop...
  • Page 646RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop...
  • Page 647RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop...
  • Page 648RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop...
  • Page 649RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0...
  • Page 650RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0...
  • Page 651RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0...
  • Page 652RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0...
  • Page 653RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6...
  • Page 654RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a...
  • Page 655RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate...
  • Page 656RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a...
  • Page 657RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.6 Timing Charts When using the I2C bus mode, the master device outputs an...
  • Page 658RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master,...
  • Page 659RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data...
  • Page 660RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master,...
  • Page 661RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in...
  • Page 662RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master,...
  • Page 663RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition...
  • Page 664RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master,...
  • Page 665RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The following describes the operations in Figure 13-32 (4) Data ~ restart condition ~...
  • Page 666RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master,...
  • Page 667RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data...
  • Page 668RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master,...
  • Page 669RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in...
  • Page 670RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock and 9-Clock Wait Is Selected...
  • Page 671RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition...
  • Page 672: CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATORRL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and...
  • Page 673 RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR <R> Figure 14-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator Internal bus Multiply- Multiplication...
  • Page 674RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.2.1 Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the...
  • Page 675RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.2.2 Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the...
  • Page 676RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.2.3 Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used...
  • Page 677RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed,...
  • Page 678 RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by...
  • Page 679RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Notes 1. Bits 1 and 2 are read-only bits. 2. The DIVST bit can...
  • Page 680RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4 Operations of Multiplier and Divider/Multiply-Accumulator 14.4.1 Multiplication (unsigned) operation • Initial setting <1>...
  • Page 681RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.2 Multiplication (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC)...
  • Page 682RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.3 Multiply-accumulation (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC)...
  • Page 683RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 × 3 + 3 =...
  • Page 684RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.4 Multiply-accumulation (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC)...
  • Page 685 RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation (2 × 3 + (−4)...
  • Page 686RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.5 Division operation • Initial setting <1> Set the multiplication/division control register (MDUC) to...
  • Page 687 Figure 14-10. Timing Diagram of Division Operation (Example: 35 ÷ 6 = 5, Remainder 5) RL78/G1A Jul 04, 2013...
  • Page 688: CHAPTER 15 DMA CONTROLLER RL78/G1A CHAPTER 15 DMA CONTROLLER CHAPTER 15 DMA CONTROLLER The RL78/G1A has an internal DMA (Direct Memory Access) controller....
  • Page 689RL78/G1A CHAPTER 15 DMA CONTROLLER 15.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 15-1. Configuration...
  • Page 690RL78/G1A CHAPTER 15 DMA CONTROLLER 15.2.2 DMA RAM address register n (DRAn) This is a 16-bit register that is used...
  • Page 691RL78/G1A CHAPTER 15 DMA CONTROLLER 15.2.3 DMA byte count register n (DBCn) This is a 10-bit register that is used...
  • Page 692RL78/G1A CHAPTER 15 DMA CONTROLLER 15.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. • DMA...
  • Page 693RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH...
  • Page 694RL78/G1A CHAPTER 15 DMA CONTROLLER 15.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is...
  • Page 695RL78/G1A CHAPTER 15 DMA CONTROLLER 15.4 Operation of DMA Controller 15.4.1 Operation procedure <1> The DMA controller is enabled to...
  • Page 696RL78/G1A CHAPTER 15 DMA CONTROLLER 15.4.2 Transfer mode The following four modes can be selected for DMA transfer by using...
  • Page 697RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5 Example of Setting of DMA Controller 15.5.1 CSI consecutive transmission A flowchart showing an...
  • Page 698RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 =...
  • Page 699RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for...
  • Page 700RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1...
  • Page 701 RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting...
  • Page 702RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is...
  • Page 703RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.5 Forced termination by software After the DSTn bit is set to 0 by software,...
  • Page 704RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-11. Forced Termination of DMA Transfer (2/2) Example 3 • Procedure for forcibly terminating...
  • Page 705RL78/G1A CHAPTER 15 DMA CONTROLLER 15.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request...
  • Page 706 RL78/G1A CHAPTER 15 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is...
  • Page 707 RL78/G1A CHAPTER 15 DMA CONTROLLER (6) Operation if instructions for accessing the data flash area <R> If the data...
  • Page 708: CHAPTER 16 INTERRUPT FUNCTIONSRL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS CHAPTER 16 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When...
  • Page 709RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (1/3) Default Priority Type Configuration Basic Interrupt Interrupt Source Internal/...
  • Page 710RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (2/3) Default Priority Type Configuration Basic Interrupt Interrupt Source Internal/...
  • Page 711 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (3/3) Default Priority Type Configuration Basic Interrupt Interrupt Source...
  • Page 712RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK...
  • Page 713RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus...
  • Page 714RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control...
  • Page 715RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (2/4) 64-pin 48-pin 32-pin 25-pin Interrupt Interrupt...
  • Page 716 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (3/4) 64-pin 48-pin 32-pin 25-pin Interrupt...
  • Page 717RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (4/4) 64-pin 48-pin 32-pin 25-pin Interrupt Interrupt...
  • Page 718 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request...
  • Page 719 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS <R> Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L,...
  • Page 720 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS <R> Figure 16-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L,...
  • Page 721 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,...
  • Page 722 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS <R> Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L,...
  • Page 723 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3.4 External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable...
  • Page 724RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-3. Interrupt Request Signal Corresponding to EGPn and EGNn bits Detection Enable Bit Edge...
  • Page 725 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS <R> 16.3.5 Program status word (PSW) The program status word is a register used...
  • Page 726RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable...
  • Page 727RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgment Processing Algorithm Start No ××IF = 1? Yes (interrupt request...
  • Page 728 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS <R> Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC...
  • Page 729RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution....
  • Page 730 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing...
  • Page 731RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice...
  • Page 732RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not...
  • Page 733 RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is...
  • Page 734: CHAPTER 17 KEY INTERRUPT FUNCTIONRL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION CHAPTER 17 KEY INTERRUPT FUNCTION The number of key interrupt input channels differs, depending...
  • Page 735RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 17-2....
  • Page 736RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION Figure 17-1. Block Diagram of Key Interrupt 0 0 KR0 1 KRF0 1 KREG...
  • Page 737RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt The key interrupt function is controlled by the following...
  • Page 738RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.2 Key return mode registers 0, 1 (KRM0, KRM1) These registers set the key...
  • Page 739RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.3 Key return flag register (KRF) This register controls the key interrupt flags (KRF0...
  • Page 740 RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.4 Port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2,...
  • Page 741RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.5 Peripheral I/O redirection register (PIOR) This register is used to specify whether to...
  • Page 742RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.4 Key Interrupt Operation 17.4.1 When not using the key interrupt flag (KRMD =...
  • Page 743RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.4.2 When using the key interrupt flag (KRMD = 1) A key interrupt (INTKR)...
  • Page 744RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION The operation when a valid edge is input to multiple key interrupt input pins...
  • Page 745RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION The operation when a valid edge is input to the KR6 to KR9 pins...
  • Page 746: CHAPTER 18 STANDBY FUNCTIONRL78/G1A CHAPTER 18 STANDBY FUNCTION CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function The standby function reduces the operating current of...
  • Page 747 RL78/G1A CHAPTER 18 STANDBY FUNCTION 18.2 Registers Controlling Standby Function The registers which control the standby function are described...
  • Page 748RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is...
  • Page 749RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is...
  • Page 750RL78/G1A CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources....
  • Page 751 RL78/G1A CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode...
  • Page 752 RL78/G1A CHAPTER 18 STANDBY FUNCTION Figure 18-2. HALT Mode Release by Reset (2/2) (3) When subsystem clock is used...
  • Page 753RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed...
  • Page 754 RL78/G1A CHAPTER 18 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two...
  • Page 755 RL78/G1A CHAPTER 18 STANDBY FUNCTION Figure 18-3. STOP Mode Release by Interrupt Request Generation (2/2) <R> (2) When high-speed...
  • Page 756 RL78/G1A CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode...
  • Page 757RL78/G1A CHAPTER 18 STANDBY FUNCTION 18.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only...
  • Page 758 RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-3. Operating Statuses in SNOOZE Mode STOP Mode Setting When Inputting CSIp/UARTq Data...
  • Page 759 RL78/G1A CHAPTER 18 STANDBY FUNCTION <R> (2) Timing diagram when the interrupt request signal is generated in the SNOOZE...
  • Page 760: CHAPTER 19 RESET FUNCTION RL78/G1A CHAPTER 19 RESET FUNCTION CHAPTER 19 RESET FUNCTION The following seven operations are available to generate a reset...
  • Page 761 Figure 19-1. Block Diagram of Reset Function Internal bus RL78/G1A Jul 04, 2013 Reset control flag register (RESF) TRAP...
  • Page 762 RL78/G1A CHAPTER 19 RESET FUNCTION 19.1 Timing of Reset Operation This LSI is reset by input of the low...
  • Page 763 RL78/G1A CHAPTER 19 RESET FUNCTION Notes 1. When P130 is set to high-level output before reset is effected, the...
  • Page 764 RL78/G1A CHAPTER 19 RESET FUNCTION 19.2 States of Operation During Reset Periods Table 19-1 shows the states of operation...
  • Page 765RL78/G1A CHAPTER 19 RESET FUNCTION Remark fIH: High-speed on-chip oscillator clock fX: X1 oscillation clock fEX: External main system clock...
  • Page 766 RL78/G1A CHAPTER 19 RESET FUNCTION 19.3 Register for Confirming Reset Source 19.3.1 Reset control flag register (RESF) Many internal...
  • Page 767 RL78/G1A CHAPTER 19 RESET FUNCTION The status of the RESF register when a reset request is generated is shown...
  • Page 768 RL78/G1A CHAPTER 19 RESET FUNCTION <R> Figure 19-5. Procedure for Checking Reset Source After reset acceptance Read the RESF...
  • Page 769: CHAPTER 20 POWER-ON-RESET CIRCUIT RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT CHAPTER 20 POWER-ON-RESET CIRCUIT 20.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has...
  • Page 770RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT 20.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in...
  • Page 771 RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage...
  • Page 772 RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage...
  • Page 773 RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage...
  • Page 774: CHAPTER 21 VOLTAGE DETECTOR RL78/G1A CHAPTER 21 VOLTAGE DETECTOR CHAPTER 21 VOLTAGE DETECTOR 21.1 Functions of Voltage Detector The operation mode and detection...
  • Page 775 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown...
  • Page 776 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable...
  • Page 777 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This...
  • Page 778 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Table 21-1. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H 7 6...
  • Page 779 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Table 21-1. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H 7 6...
  • Page 780 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.4 Operation of Voltage Detector <R> 21.4.1 When used as reset mode Specify the...
  • Page 781 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR <R> Figure 21-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1,...
  • Page 782 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR <R> 21.4.2 When used as interrupt mode Specify the operation mode (the interrupt mode...
  • Page 783 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR <R> Figure 21-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1,...
  • Page 784 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR <R> 21.4.3 When used as interrupt & reset mode Specify the operation mode (the...
  • Page 785 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR <R> Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option...
  • Page 786RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. 2. After...
  • Page 787 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR <R> Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option...
  • Page 788 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. 2....
  • Page 789 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection...
  • Page 790 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.5 Cautions for Voltage Detector <R> (1) Voltage fluctuation when power is supplied In...
  • Page 791 RL78/G1A CHAPTER 21 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD...
  • Page 792: CHAPTER 22 SAFETY FUNCTIONS RL78/G1A CHAPTER 22 SAFETY FUNCTIONS CHAPTER 22 SAFETY FUNCTIONS 22.1 Overview of Safety Functions The following safety functions are...
  • Page 793RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.2 Registers Used by Safety Functions The safety functions use the following registers for each...
  • Page 794RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-1. Format of Flash Memory CRC Control Register (CRC0CTL) Address: F02F0H After reset: 00H...
  • Page 795 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS <Operation flow> <R> Figure 22-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC)...
  • Page 796RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.2 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508...
  • Page 797RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.2.2 CRC data register (CRCD) This register is used to store the CRC operation result...
  • Page 798RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.3 RAM parity error detection function The IEC60730 standard mandates the checking of RAM data....
  • Page 799 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS <R> Figure 22-8. Flowchart of RAM Parity Check Start of check Yes RPERF =...
  • Page 800 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard...
  • Page 801RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates...
  • Page 802 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU...
  • Page 803RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Products Code Flash Memory RAM Detected Lowest Address for (00000H to xxxxxH) (zzzzzH to FFEFFH)...
  • Page 804 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is...
  • Page 805 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.7.1 Timer input select register 0 (TIS0) <R> The TIS0 register is used to...
  • Page 806 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.8 A/D test function <R> The IEC60730 standard mandates testing the A/D converter. The...
  • Page 807 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS <R> Figure 22-15. Configuration of A/D Test Function • ADISS • ADS4 to ADS0...
  • Page 808 RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.8.1 A/D test register (ADTES) <R> This register is used to select the A/D...
  • Page 809RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-17. Format of Analog Input Channel Specification Register (ADS) (1/2) Address: FFF31H After reset:...
  • Page 810RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Select input...
  • Page 811: CHAPTER 23 REGULATORRL78/G1A CHAPTER 23 REGULATOR CHAPTER 23 REGULATOR 23.1 Regulator Overview The RL78/G1A contains a circuit for operating the device with...
  • Page 812: CHAPTER 24 OPTION BYTE RL78/G1A CHAPTER 24 OPTION BYTE CHAPTER 24 OPTION BYTE 24.1 Functions of Option Bytes Addresses 000C0H to 000C3H of...
  • Page 813 RL78/G1A CHAPTER 24 OPTION BYTE (3) 000C2H/010C2H { Setting of flash operation mode • LV (low voltage main) mode...
  • Page 814RL78/G1A CHAPTER 24 OPTION BYTE 24.2 Format of User Option Byte The format of user option byte is shown below....
  • Page 815 RL78/G1A CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H 7 6...
  • Page 816 RL78/G1A CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H 7 6...
  • Page 817 RL78/G1A CHAPTER 24 OPTION BYTE Figure 24-3. Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H 7 6 5 4...
  • Page 818RL78/G1A CHAPTER 24 OPTION BYTE 24.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is...
  • Page 819 RL78/G1A CHAPTER 24 OPTION BYTE 24.4 Setting of Option Byte <R> The user option byte and on-chip debug option...
  • Page 820: CHAPTER 25 FLASH MEMORYRL78/G1A CHAPTER 25 FLASH MEMORY CHAPTER 25 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program...
  • Page 821 RL78/G1A CHAPTER 25 FLASH MEMORY The following methods for programming the flash memory are available. <R> The code flash...
  • Page 822RL78/G1A CHAPTER 25 FLASH MEMORY 25.1 Serial Programming Using Flash Memory Programmer The following dedicated flash memory programmer can be...
  • Page 823 RL78/G1A CHAPTER 25 FLASH MEMORY <R> Table 25-1. Wiring between RL78/G1A and Dedicated Flash Memory Programmer Pin Configuration of...
  • Page 824 RL78/G1A CHAPTER 25 FLASH MEMORY 25.1.1 Programming environment The environment required for writing a program to the flash memory...
  • Page 825 RL78/G1A CHAPTER 25 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See...
  • Page 826 RL78/G1A CHAPTER 25 FLASH MEMORY 25.2.2 Communication mode Communication between the external device and the RL78 microcontroller is established...
  • Page 827 RL78/G1A CHAPTER 25 FLASH MEMORY 25.3 Connection of Pins on Board To write the flash memory on-board by using...
  • Page 828 RL78/G1A CHAPTER 25 FLASH MEMORY 25.3.3 Port pins When the flash memory programming mode is set, all the pins...
  • Page 829RL78/G1A CHAPTER 25 FLASH MEMORY 25.4 Serial Programming Method 25.4.1 Serial programming procedure The following figure illustrates a flow for...
  • Page 830 RL78/G1A CHAPTER 25 FLASH MEMORY 25.4.2 Flash memory programming mode To rewrite the contents of the code flash memory...
  • Page 831 RL78/G1A CHAPTER 25 FLASH MEMORY There are two flash memory programming modes: wide voltage mode and full speed mode....
  • Page 832 RL78/G1A CHAPTER 25 FLASH MEMORY 25.4.3 Selecting communication mode Communication modes of the RL78 microcontroller are as follows. Table...
  • Page 833RL78/G1A CHAPTER 25 FLASH MEMORY Product information (such as product name and firmware version) can be obtained by executing the...
  • Page 834 RL78/G1A CHAPTER 25 FLASH MEMORY <R> 25.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)...
  • Page 835 RL78/G1A CHAPTER 25 FLASH MEMORY <R> 25.6 Self-Programming The RL78 microcontroller supports a self-programming function that can be used...
  • Page 836RL78/G1A CHAPTER 25 FLASH MEMORY 25.6.1 Self-programming procedure The following figure illustrates a flow for rewriting the code flash memory...
  • Page 837RL78/G1A CHAPTER 25 FLASH MEMORY 25.6.2 Boot swap function If rewriting the boot area failed by temporary power failure or...
  • Page 838RL78/G1A CHAPTER 25 FLASH MEMORY Figure 25-10. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5...
  • Page 839RL78/G1A CHAPTER 25 FLASH MEMORY 25.6.3 Flash shield window function The flash shield window function is provided as one of...
  • Page 840 RL78/G1A CHAPTER 25 FLASH MEMORY 25.7 Security Settings The RL78 microcontroller supports a security function that prohibits rewriting the...
  • Page 841 RL78/G1A CHAPTER 25 FLASH MEMORY Table 25-12. Relationship Between Enabling Security Function and Command (1) During serial programming Valid...
  • Page 842 RL78/G1A CHAPTER 25 FLASH MEMORY 25.8 Data Flash 25.8.1 Data flash overview An overview of the data flash memory...
  • Page 843 RL78/G1A CHAPTER 25 FLASH MEMORY 25.8.3 Procedure for accessing data flash memory The data flash memory is stopped after...
  • Page 844: CHAPTER 26 ON-CHIP DEBUG FUNCTION RL78/G1A CHAPTER 26 ON-CHIP DEBUG FUNCTION CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.1 Connecting E1 On-Chip Debugging Emulator The RL78...
  • Page 845RL78/G1A CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.2 On-Chip Debug Security ID The RL78 microcontroller has an on-chip debug operation control...
  • Page 846RL78/G1A CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-2. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal...
  • Page 847: CHAPTER 27 BCD CORRECTION CIRCUITRL78/G1A CHAPTER 27 BCD CORRECTION CIRCUIT CHAPTER 27 BCD CORRECTION CIRCUIT 27.1 BCD Correction Circuit Function The result of addition/subtraction...
  • Page 848RL78/G1A CHAPTER 27 BCD CORRECTION CIRCUIT 27.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is...
  • Page 849RL78/G1A CHAPTER 27 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD...
  • Page 850: CHAPTER 28 INSTRUCTION SET RL78/G1A CHAPTER 28 INSTRUCTION SET CHAPTER 28 INSTRUCTION SET <R> This chapter lists the instructions in the RL78 microcontroller...
  • Page 851RL78/G1A CHAPTER 28 INSTRUCTION SET 28.1.2 Description of operation column The operation when the instruction is executed is shown in...
  • Page 852RL78/G1A CHAPTER 28 INSTRUCTION SET 28.1.3 Description of flag operation column The change of the flag value when the instruction...
  • Page 853 RL78/G1A CHAPTER 28 INSTRUCTION SET 28.2 Operation List Table 28-5. Operation List (1/17) Instruction Mnemonic Operands Bytes Clocks Clocks...
  • Page 854 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 855 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 856 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 857 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 858 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 859 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 860 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 861 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 862 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 863 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 864 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 865 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 866 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 867 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 868 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (16/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 869 RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Clocks Clocks Flag Group Note...
  • Page 870: CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85 degree)RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) This...
  • Page 871RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C)...
  • Page 872RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Symbols Conditions...
  • Page 873 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.2 Oscillator Characteristics 29.2.1 X1, XT1 oscillator characteristics (TA...
  • Page 874RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.3 DC Characteristics 29.3.1 Pin characteristics (TA = −40 to...
  • Page 875RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤...
  • Page 876RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤...
  • Page 877RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤...
  • Page 878RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤...
  • Page 879RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.3.2 Supply current characteristics (TA = −40 to +85°C, 1.6...
  • Page 880RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) Notes 1. Total current flowing into VDD and EVDD0, including...
  • Page 881RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤...
  • Page 882RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) Notes 1. Total current flowing into VDD and EVDD0, including...
  • Page 883 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> (TA = −40 to +85°C, 1.6 V ≤...
  • Page 884 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> Notes 1. Current flowing to VDD. 2. When...
  • Page 885RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.4 AC Characteristics (TA = −40 to +85°C, AVDD ≤...
  • Page 886 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) Note The following conditions are required for low-voltage interface...
  • Page 887 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> TCY vs VDD (LS (low-speed main) mode) 10...
  • Page 888 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) AC Timing Test Points VIH/VOH VIH/VOH Test points <R>...
  • Page 889RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RESET Input Timing tRSL RESET R01UH0305EJ0200 Rev.2.00 869 Jul 04,...
  • Page 890 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH...
  • Page 891RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) UART mode connection diagram (during communication at same potential) TxDq...
  • Page 892RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (2) During communication at same potential (CSI mode) (master mode,...
  • Page 893RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (3) During communication at same potential (CSI mode) (master mode,...
  • Page 894RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (4) During communication at same potential (CSI mode) (slave mode,...
  • Page 895RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) Notes 1. HS is condition of HS (high-speed main) mode....
  • Page 896RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) CSI mode connection diagram (during communication at same potential) SCKp...
  • Page 897RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 2 (5) During communication at same potential (simplified I C...
  • Page 898RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 2 (5) During communication at same potential (simplified I C...
  • Page 899 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V)...
  • Page 900 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V)...
  • Page 901RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) UART mode connection diagram (during communication at different potential) Vb...
  • Page 902 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (7) Communication at different potential (2.5 V) (CSI mode)...
  • Page 903 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (8) Communication at different potential (1.8V, 2.5 V) (CSI...
  • Page 904 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V)...
  • Page 905RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) CSI mode connection diagram (during communication at different potential) <Master>...
  • Page 906RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) CSI mode serial transfer timing (master mode) (during communication at...
  • Page 907 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (9) Communication at different potential (1.8 V, 2.5 V)...
  • Page 908RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) CSI mode connection diagram (during communication at different potential) <Slave>...
  • Page 909RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) CSI mode serial transfer timing (slave mode) (during communication at...
  • Page 910RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 2 (10) Communication at different potential (1.8 V, 2.5 V)...
  • Page 911 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 2 (10) Communication at different potential (1.8 V, 2.5...
  • Page 912RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 2 Simplified I C mode connection diagram (during communication at...
  • Page 913RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.5.2 Serial interface IICA 2 (1) I C standard mode...
  • Page 914RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) (2) I2C fast mode, fast mode plus (TA = −40...
  • Page 915RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) IICA serial transfer timing tLOW SCL0 tHD:DAT tHIGH tSU:STA tHD:STA...
  • Page 916 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.6 Analog Characteristics 29.6.1 A/D converter characteristics Division of...
  • Page 917 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1...
  • Page 918 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> (3) When reference voltage (+) = AVDD (ADREFP1...
  • Page 919 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> (4) When reference voltage (+) = AVREFP/ANI0 (ADREFP1...
  • Page 920 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> (5) When reference voltage (+) = AVDD (ADREFP1...
  • Page 921 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) <R> (6) When reference voltage (+) = Internal reference...
  • Page 922RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode...
  • Page 923RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) LVD Detection Voltage of Interrupt & Reset Mode (TA =...
  • Page 924 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.7 Data Memory STOP Mode Low Supply Voltage Data...
  • Page 925 RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) 29.10 Timing Specs for Switching Flash Memory Programming Modes...
  • Page 926: CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105 degree)RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS...
  • Page 927RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.1 Absolute Maximum Ratings Absolute Maximum Ratings...
  • Page 928RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Absolute Maximum Ratings (TA = 25°C) (2/2)...
  • Page 929 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.2 Oscillator Characteristics 30.2.1 X1, XT1...
  • Page 930 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.3 DC Characteristics 30.3.1 Pin characteristics...
  • Page 931 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> (TA = −40 to +105°C,...
  • Page 932RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V...
  • Page 933RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V...
  • Page 934RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V...
  • Page 935RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.3.2 Supply current characteristics (TA = −40...
  • Page 936RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Notes 1. Total current flowing into VDD...
  • Page 937RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V...
  • Page 938RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Notes 1. Total current flowing into VDD...
  • Page 939RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V...
  • Page 940 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> Notes 1. Current flowing to...
  • Page 941RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.4 AC Characteristics (TA = −40 to...
  • Page 942 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Minimum Instruction Execution Time during Main...
  • Page 943 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) AC Timing Test Points VIH/VOH VIH/VOH...
  • Page 944RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RESET Input Timing tRSL RESET R01UH0305EJ0200 Rev.2.00...
  • Page 945 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.5 Peripheral Functions Characteristics AC Timing...
  • Page 946RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (2) During communication at same potential (CSI...
  • Page 947 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> (3) During communication at same...
  • Page 948RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode connection diagram (during communication at...
  • Page 949RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 (4) During communication at same potential...
  • Page 950RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 Simplified I C mode mode connection...
  • Page 951 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (5) Communication at different potential (1.8...
  • Page 952 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (5) Communication at different potential (1.8...
  • Page 953RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) UART mode connection diagram (during communication at...
  • Page 954 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (6) Communication at different potential (1.8...
  • Page 955 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (6) Communication at different potential (1.8...
  • Page 956RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode serial transfer timing (master mode)...
  • Page 957 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (7) Communication at different potential (1.8...
  • Page 958RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode connection diagram (during communication at...
  • Page 959RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode serial transfer timing (slave mode)...
  • Page 960RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 (8) Communication at different potential (1.8...
  • Page 961 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 (8) Communication at different potential...
  • Page 962RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 Simplified I C mode connection diagram...
  • Page 963RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.5.2 Serial interface IICA 2 (1) I...
  • Page 964 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.6 Analog Characteristics 30.6.1 A/D converter...
  • Page 965 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> (2) When reference voltage (+)...
  • Page 966 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> (3) When reference voltage (+)...
  • Page 967 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> (4) When reference voltage (+)...
  • Page 968 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) <R> (5) When reference voltage (+)...
  • Page 969RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.6.4 LVD circuit characteristics LVD Detection Voltage...
  • Page 970 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.7 Data Memory STOP Mode Low...
  • Page 971 RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.10 Timing Specs for Switching Flash...
  • Page 972: CHAPTER 31 PACKAGE DRAWINGS RL78/G1A CHAPTER 31 PACKAGE DRAWINGS CHAPTER 31 PACKAGE DRAWINGS <R> 31.1 25-pin Products R5F10E8AALA, R5F10E8CALA, R5F10E8DALA, R5F10E8EALA JEITA Package...
  • Page 973 RL78/G1A CHAPTER 31 PACKAGE DRAWINGS <R> 31.2 32-pin Products R5F10EBAANA, R5F10EBCANA, R5F10EBDANA, R5F10EBEANA R5F10EBAGNA, R5F10EBCGNA, R5F10EBDGNA, R5F10EBEGNA JEITA Package...
  • Page 974 RL78/G1A CHAPTER 31 PACKAGE DRAWINGS <R> 31.3 48-pin Products R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB, R5F10EGEAFB R5F10EGAGFB, R5F10EGCGFB, R5F10EGDGFB, R5F10EGEGFB JEITA Package...
  • Page 975RL78/G1A CHAPTER 31 PACKAGE DRAWINGS R5F10EGAANA, R5F10EGCANA, R5F10EGDANA, R5F10EGEANA R5F10EGAGNA, R5F10EGCGNA, R5F10EGDGNA, R5F10EGEGNA JEITA Package code RENESAS code Previous code...
  • Page 976 RL78/G1A CHAPTER 31 PACKAGE DRAWINGS <R> 31.4 64-pin Products R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB R5F10ELCGFB, R5F10ELDGFB, R5F10ELEGFB JEITA Package Code RENESAS...
  • Page 977RL78/G1A CHAPTER 31 PACKAGE DRAWINGS R5F10ELCABG, R5F10ELDABG, R5F10ELEABG JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-VFBGA64-4x4-0.40 PVBG0064LA-A...
  • Page 978: APPENDIX A REVISION HISTORYRL78/G1A APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/11) Page Description Classification R01UH0305EJ0110...
  • Page 979RL78/G1A APPENDIX A REVISION HISTORY (2/11) Page Description Classification p.110 Modification of 4.3.6 Port mode control registers (PMCxx) (c) p.111...
  • Page 980RL78/G1A APPENDIX A REVISION HISTORY (3/11) Page Description Classification p.198 Modification of 6.3.2 Timer clock select register m (TPSm) (c)...
  • Page 981RL78/G1A APPENDIX A REVISION HISTORY (4/11) Page Description Classification p.306 Modification of 7.3.10 Month count register (MONTH) (c) p.309 Modification...
  • Page 982RL78/G1A APPENDIX A REVISION HISTORY (5/11) Page Description Classification p.393 Modification of Figure 11-37. Flowchart for Setting up SNOOZE Mode...
  • Page 983RL78/G1A APPENDIX A REVISION HISTORY (6/11) Page Description Classification p.460 Modification of Figure 12-41. Initial Setting Procedure for Master (c)...
  • Page 984RL78/G1A APPENDIX A REVISION HISTORY (7/11) Page Description Classification p.514 Modification of Figure 12-82. Flowchart of UART Transmission (in Continuous...
  • Page 985RL78/G1A APPENDIX A REVISION HISTORY (8/11) Page Description Classification p.658 Modification of Figure 14-5. Format of Multiplication/Division Control Register (MDUC)...
  • Page 986RL78/G1A APPENDIX A REVISION HISTORY (9/11) Page Description Classification p.739 Modification of Figure 18-5. When the Interrupt Request Signal is...
  • Page 987RL78/G1A APPENDIX A REVISION HISTORY (10/11) Page Description Classification p.784 Modification of 22.3.7 Frequency detection function (c) p.785 Modification of...
  • Page 988RL78/G1A APPENDIX A REVISION HISTORY (11/11) Page Description Classification p.868 Modification of AC Timing Test Points and TI/TO Timing (c)...
  • Page 989RL78/G1A APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions....
  • Page 990RL78/G1A APPENDIX A REVISION HISTORY (2/5) Page Description Classification CHAPTER 5 CLOCK GENERATOR p.162 Addition of description to 5.1 (1)...
  • Page 991RL78/G1A APPENDIX A REVISION HISTORY (3/5) Page Description Classification CHAPTER 11 A/D CONVERTER p.361 Modification of Figure 11-1. Block Diagram...
  • Page 992RL78/G1A APPENDIX A REVISION HISTORY (4/5) Page Description Classification CHAPTER 18 STANDBY FUNCTION p.758 Modification of Table 18-1. Operating Statuses...
  • Page 993RL78/G1A APPENDIX A REVISION HISTORY (5/5) Page Description Classification CHAPTER 28 INSTRUCTION SET p.880 Modification of Table 28-5. Operation List...
  • Page 994RL78/G1A APPENDIX A REVISION HISTORY (1/8) Edition Description Chapter Rev.0.03 Renamed interval timer (unit) to 12-bit interval timer Though out...
  • Page 995RL78/G1A APPENDIX A REVISION HISTORY (2/8) Edition Description Chapter Rev.0.03 Addition of remark to 4.3.9 Global digital input disable register...
  • Page 996RL78/G1A APPENDIX A REVISION HISTORY (3/8) Edition Description Chapter Rev.0.03 Modification of remark 1 in Figure 6-31. Operation Timing (In...
  • Page 997RL78/G1A APPENDIX A REVISION HISTORY (4/8) Edition Description Chapter Rev.0.03 Addition of note 1 to 12.1.1 3-wire serial I/O (CSI00,...
  • Page 998RL78/G1A APPENDIX A REVISION HISTORY (5/8) Edition Description Chapter Rev.0.03 Modification of note 1 and caution 1 in Figure 12-94....
  • Page 999RL78/G1A APPENDIX A REVISION HISTORY (6/8) Edition Description Chapter Rev.0.03 Deletion of caution 2 in Figure 16-2. Format of Interrupt...
  • Page 1000RL78/G1A APPENDIX A REVISION HISTORY (7/8) Edition Description Chapter Rev.0.03 Modification of Figure 22-6. CRC Operation Function (General-Purpose CRC) CHAPTER...
  • Page 1001RL78/G1A APPENDIX A REVISION HISTORY (8/8) Edition Description Chapter Rev.0.03 Modification of description and addition of caution in 29.6.4 LVD...
  • Page 1002: ColophonRL78/G1A User’s Manual: Hardware Publication Date: Rev.2.00 Jul 04, 2013 Published by: Renesas Electronics Corporation
  • Page 1003: Address ListSALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa...
  • Page 1004: Back CoverRL78/G1A R01UH0305EJ0200