Avaya 03-300430 User Manual

For DS1- or BRI-based synchronization, a particular DS1 or PRI interface is configured as the 
synchronization reference. The IPSI/Tone-Clock board in the same PN locks on to this 
reference and regenerates clock signals that are placed on the PN’s backplane. In turn, the 
Center Stage Switch (CSS) components transfer this timing to every other PN. These IPSI/
Tone-Clocks then regenerate clock signals for their own PNs at the same rate as the:

●

Master PN

●

Public network

This creates a hierarchy where the master PN receives timing from the public network, and 
every other PN derives its timing from the master through the CSS. See 

Typically, a pair of interfaces from the public network are configured — one as a primary and 
one as a secondary. The IPSI/Tone-Clock in the Master PN can:

●

Lock onto either interface

●

Switch between them in the event of a failure

In the event of a dual failure, the Tone-Clock in the master PN can generate its own timing and 
keep every PN synchronized. However, these PNs would not be synchronized with any other 
public-network interfaces that exist in any of the PNs.
When a center stage is implemented via an ATM network, it is possible to obtain timing from the 
ATM network. For more information, See 

Master
   PN

Center

Stage
Switch

Slave
   PN

Slave
   PN

Slave
   PN

 Public
Network

Primary

Secondary