Avaya 03-300430 User Manual
ATM-SYNC (ATM Synchronization)
Issue 1 June 2005
611
Stratum 4 Synchronization
Systems may have primary and secondary synchronization references (DS1/UDS1 interface
circuit packs or ATM-Switch) when using Stratum 4 synchronization.
If the primary synchronization reference in
circuit packs or ATM-Switch) when using Stratum 4 synchronization.
If the primary synchronization reference in
on page 612 is providing a valid timing signal, then the flow of system
synchronization would travel from the DS1 interface circuit pack in the PN to the ATM switch.
The primary DS1 interface circuit pack provides a timing signal for the ATM switch clock
circuitry. This synchronization source is then distributed to all of its OC3 Interface Modules.
Each ATM Expansion Interface circuit pack uses the received data stream from the ATM switch
to generate a timing signal. The Tone-Clock circuits in the PNs use this signal to generate
timing for every circuit pack in their respective PNs. All PNs, in the above mentioned scenario
are designated the slave PNs. The ATM switch is the master that contains the system
synchronization source. If the primary synchronization reference does not provide a valid timing
signal, ATM synchronization maintenance infers a switch to the secondary reference.
If the primary synchronization reference is not providing a valid timing signal, the system
automatically switches to the secondary synchronization reference. If the primary
synchronization reference is invalid, and if the secondary reference does not provide a valid
timing signal or is not administered as a synchronization reference, the switch infers that the
local oscillator of the ATM switch provides the system timing source. If the system is using the
local oscillator of the ATM switch as the system timing source because the primary and
secondary references are providing invalid timing signals, when either the primary or secondary
reference becomes valid again, the system switches back to the primary or secondary source.
When both the primary and secondary source become valid, the system switches to the primary
source, since the primary source is always preferred over the secondary source when both
sources are equally healthy.
The primary DS1 interface circuit pack provides a timing signal for the ATM switch clock
circuitry. This synchronization source is then distributed to all of its OC3 Interface Modules.
Each ATM Expansion Interface circuit pack uses the received data stream from the ATM switch
to generate a timing signal. The Tone-Clock circuits in the PNs use this signal to generate
timing for every circuit pack in their respective PNs. All PNs, in the above mentioned scenario
are designated the slave PNs. The ATM switch is the master that contains the system
synchronization source. If the primary synchronization reference does not provide a valid timing
signal, ATM synchronization maintenance infers a switch to the secondary reference.
If the primary synchronization reference is not providing a valid timing signal, the system
automatically switches to the secondary synchronization reference. If the primary
synchronization reference is invalid, and if the secondary reference does not provide a valid
timing signal or is not administered as a synchronization reference, the switch infers that the
local oscillator of the ATM switch provides the system timing source. If the system is using the
local oscillator of the ATM switch as the system timing source because the primary and
secondary references are providing invalid timing signals, when either the primary or secondary
reference becomes valid again, the system switches back to the primary or secondary source.
When both the primary and secondary source become valid, the system switches to the primary
source, since the primary source is always preferred over the secondary source when both
sources are equally healthy.
depicts a simplex ATM PNC with T1/OC3 synchronization reference into the ATM
switch.