Intel 315889-002 User Manual

56

315889-002

1. Select type and number of bulk capacitors. Normally the equivalent ESR needs to 

be approximately ½ the load line target impedance. For a 1.25 m

Ω

 load line, the 

equivalent ESR should be less than 0.625 m

Ω

. The reason for selecting the number 

of bulk capacitors to yield an equivalent ESR to be ½ the target impedance is to 

compensate for the parasitic resistance of the PCB layout plane shapes and for 

aging of the capacitors. This is a starting point for the design. The final number of 

bulk capacitors will be determined by transient droop testing and Z(f) 

measurements.

2. The type and number of MLCC capacitors in the socket cavity is specified in the 

. These are required to meet both power delivery impedance and 

signal integrity issues.

3. Design the PWM loop bandwidth compensation. The ideal loop BW is set at the 

frequency where the bulk capacitor impedance meets the target impedance curve. 
In 

, it is approximately 30 kHz. Small increases in the loop bandwidth will 

not improve system performance until the bandwidth is moved to where the MLCC 
impedance meets the target impedance at ~ 700 kHz which is impractical.

Consult the PWM chip manufacturer's data sheets and application notes on calculating 
the PWM loop compensation and AVP programming values.

 

10

-3

10

-2

10

-1

10

0

10

1

0

1

2

3

4

5

6

7

8

9

10

frequency(MHz)

im

pe

d

a

nc

e (

m

oh

m

s

)

measured vs simulated results

meas:allcaps
meas:bank1-9+2oscons
sim:swvr-allcaps
sim:avgvr-allcaps
sim:swvr-bank1-9+2osc
sim:avgvr-bank1-9+2osc