Intel X3480 BV80605002505AH Data Sheet

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

69

BR0#

Input/Output

BR0# drives the BREQ0# signal in the system and is used by the 

processor to request the bus. During power-on configuration this 

signal is sampled to determine the agent ID = 0. 
This signal does not have on-die termination and must be terminated.

BSEL[2:0]

Output

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select 

the processor input clock frequency. 

 defines the possible 

combinations of the signals and the frequency associated with each 

combination. The required frequency is determined by the processor, 

chipset and clock synthesizer. All agents must operate at the same 

frequency. For more information about these signals, including 

termination recommendations refer to 

. 

COMP8
COMP[3:0]

Analog

COMP[3:0] and COMP8 must be terminated to V

SS 

on the system 

board using precision resistors. 

D[63:0]#

Input/Output

D[63:0]# (Data) are the data signals. These signals provide a 64-bit 

data path between the processor FSB agents, and must connect the 

appropriate pins/lands on all such agents. The data driver asserts 

DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four 

times in a common clock period. D[63:0]# are latched off the falling 

edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data 

signals correspond to a pair of one DSTBP# and one DSTBN#. The 

following table shows the grouping of data signals to data strobes and 

DBI#.

Furthermore, the DBI# signals determine the polarity of the data 

signals. Each group of 16 data signals corresponds to one DBI# signal. 

When the DBI# signal is active, the corresponding data group is 

inverted and therefore sampled active high. 

DBI[3:0]#

Input/Output

DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate 

the polarity of the D[63:0]# signals.The DBI[3:0]# signals are 

activated when the data on the data bus is inverted. If more than half 

the data bits, within a 16-bit group, would have been asserted 

electrically low, the bus agent may invert the data bus signals for that 

particular sub-phase for that 16-bit group.

DBR#

Output

DBR# (Debug Reset) is used only in processor systems where no 

debug port is implemented on the system board. DBR# is used by a 

debug port interposer so that an in-target probe can drive system 

reset. If a debug port is implemented in the system, DBR# is a no 

connect in the system. DBR# is not a processor signal.

DBSY#

Input/Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for 

driving data on the processor FSB to indicate that the data bus is in 

use. The data bus is released after DBSY# is de-asserted. This signal 

must connect the appropriate pins/lands on all processor FSB agents.

Quad-Pumped Signal Groups

D[15:0]#

0

0

D[31:16]#

1

1

D[47:32]#

2

2

D[63:48]#

3

3

DBI[3:0] Assignment To Data Bus 

DBI3#

D[63:48]#

DBI2#

D[47:32]#

DBI1#

D[31:16]#

DBI0#

D[15:0]#