Intel N475 AU80610006240AA User Manual
Product codes
AU80610006240AA
Datasheet
33
Functional Description
1’s and 0’s are represented the differential voltage between the pair of signals.
3.2.5.2.2
LVDS Pair States
The LVDS pairs can be put into one of five states, powered down tri-state, powered
down 0 V, common mode, send 0’s, or active. When in powered down state, the circuit
enters a low power state and drives out 0 V or tri-states on both the output pins for the
entire channel. The common mode tri-state is both pins of the pair set to the common
mode voltage. When in the send 0’s state, the circuit is powered up but sends only 0 for
the pixel color data regardless what the actual data is with the clock lines and timing
signals sending the normal clock and timing data.
down 0 V, common mode, send 0’s, or active. When in powered down state, the circuit
enters a low power state and drives out 0 V or tri-states on both the output pins for the
entire channel. The common mode tri-state is both pins of the pair set to the common
mode voltage. When in the send 0’s state, the circuit is powered up but sends only 0 for
the pixel color data regardless what the actual data is with the clock lines and timing
signals sending the normal clock and timing data.
Figure 3-2. LVDS Signals and Swing Voltage
Figure 3-3. LVDS Clock and Data Relationship