Intel N475 AU80610006240AA User Manual

Product codes
AU80610006240AA
Page of 85
Datasheet
31
Functional Description
3.2.4
Display Pipes
The display consists of two pipes: 
Display Pipe A (VGA)
Display Pipe B (VGA or LVDS)
A pipe consists of a set of combined planes and a timing generator. The timing 
generators provide the basic timing information for each of the display pipes. The GPU 
has two display pipes, allowing for support of two independent display streams. A port 
is the destination for the result of the pipe.
3.2.4.1
Clock Generator Units (DPLLs)
The clock generator units provide a stable frequency for driving display devices. It 
operates by converting an input reference frequency into an output frequency. The 
timing generators take their input from internal DPLL devices that are programmable to 
generate pixel clocks in the range of 20 MHz–200 MHz. Accuracy for VESA timing 
modes is required to be within ±0.5%.
The DPLL can take a reference frequency from the external reference inputs 
(REFCLKINN/P, REFSSCLKINN/P).
3.2.5
Display Ports
Display ports are the destination for the display pipes. These are the places where the 
data finally appears to devices outside the graphics device. the GPU has one CRT 
display port (Analog) and one dedicated LVDS port (Digital).
3.2.5.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC 
signal. There is an associated DDC signal pair that is implemented using GPIO pins 
dedicated to the analog port. The intended target device is for a CRT based monitor 
with a VGA connector. Display devices such as LCD panels with analog inputs may work 
satisfactory but no functionality added to the signals to enhance that capability.
Table 3-17.Analog Port Characteristics
Signal
Port Characteristics
Support
RGB
Voltage Range
0.7 Vp-p only
Monitor Sense
Analog Compare
Analog Copy Protection
No
Sync on Green
No