Intel N455 AU80610006237AA User Manual

Product codes
AU80610006237AA
Page of 85
Signal Description
16
Datasheet
FERR#
FERR# (Floating-point Error) is a multiplexed signal 
and its meaning is qualified with STPCLK#. When 
STPCLK# is not asserted, FERR# indicates a floating 
point when the processor detects an unmasked 
floating-point error. FERR# is similar to the ERROR# 
signal on the Intel 387 coprocessor, and is included 
for compatibility with systems using MSDOS*- type 
floating-point error reporting. When STPCLK# is 
asserted, an assertion of FERR# indicates that the 
processor has a pending break event waiting for 
service. The assertion of FERR# indicates that the 
processor should be returned to the Normal state. 
When FERR# is asserted, indicating a break event, it 
will remain asserted until STPCLK# is deasserted. 
Assertion of PREQ# when STPCLK# is active will also 
cause an FERR# break event. 
For additional information on the pending break 
event functionality, including identification of 
support of the feature and enable/disable 
information, refer to Volume 3 of the Intel® 64 and 
IA-32 Architectures Software Developer's Manuals 
and the Intel® Processor Identification and CPUID 
Instruction Application Note
.
O
Core
Open 
Drain
GTLREF
Reference voltage for BPM* pins.
I
Core
Analog
IGNNE#
IGNNE# (Ignore Numeric Error) is asserted to force 
the processor to ignore a numeric error and continue 
to execute non-control floating-point instructions. If 
IGNNE# is deasserted, the processor generates an 
exception on a non-control floating-point instruction 
if a previous floating-point instruction caused an 
error. IGNNE# has no effect when the NE bit in 
control register 0 (CR0) is set.
I
Core
CMOS
INIT#
INIT# (Initialization), when asserted, resets integer 
registers inside the processor without affecting its 
internal caches or floating-point registers. The 
processor then begins execution at the power-on 
Reset vector configured during power-on 
configuration. The processor continues to handle 
snoop requests during INIT# assertion.
I
Core
CMOS
Table 2-3. Processor Legacy Signals
Signal Name
Description 
Direction
Type