Intel N455 AU80610006237AA User Manual

Datasheet

17

LINT0, LINT1

LINT[1:0] (Local APIC Interrupt) must connect the 
appropriate pins of all APIC Bus agents. When the 
APIC is disabled, the LINT0 signal becomes INTR, a 
maskable interrupt request signal, and LINT1 
becomes NMI, a non-maskable interrupt. INTR and 
NMI are backward compatible with the signals of 
those names on the Pentium processor. 
Both of these signals must be software configured 
via BIOS programming of the APIC register space to 
be used either as NMI/INTR or LINT0/LINT1. 
Because the APIC is enabled by default after Reset, 
operation of these pins as LINT0/LINT1 is the default 
configuration.

I

Core

CMOS

SMI#

SMI# (System Management Interrupt) is asserted 
asynchronously by system logic. On accepting a 
System Management Interrupt, the processor saves 
the current state and enter System Management 
Mode (SMM). An SMI Acknowledge transaction is 
issued, and the processor begins program execution 
from the SMM handler. If SMI# is asserted during 
the deassertion of RESET# the processor will tristate 
its outputs.

I

Core

CMOS

STPCLK#

Stop clock, when asserted, causes the processor to 
enter a low power Stop-Grant state. The processor 
issues a Stop-Grant Acknowledge transaction, and 
stops providing internal clock signals to all processor 
core units. The processor continues to snoop bus 
transactions and service interrupts while in Stop-
Grant state. When STPCLK# is deasserted, the 
processor restarts its internal clock to all units and 
resumes execution.

I

Core

CMOS

THERMDA_1
THERMDC_1

Thermal Diode - Anode & Cathode of the processor.

I

O

Core

Analog

THERMDA_2/RSVD
THERMDC_2/RSVD

Reserved pins of Thermal Diode.

I

O

Core

Analog

BPM_1#[3:0]
BPM_2#[3:0]/
RSVD

Breakpoint and Performance Monitor Signals: Output 
from the processor that indicate the status of 
breakpoints and programmable counters used for 
monitoring processor performance.
BPM_2#[3:0]/RSVD are reserved pins.

I/O

GTL+

PRDY#

PRDY# is a processor output used by debug tools to 
determine processor debug readiness.

O

Asynch 

GTL+

PREQ#

PREQ# is used by debug tools to request debug 
operation of the processor.

I

Asynch 

GTL+