Intel N455 AU80610006237AA User Manual
Product codes
AU80610006237AA
Functional Description
32
Datasheet
3.2.5.1.1
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for
the CRT monitor. GPU’s integrated RAMDAC supports resolutions up to 1400 x 1050
@ 60 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.
transforms the digital data from the graphics and video subsystems to analog data for
the CRT monitor. GPU’s integrated RAMDAC supports resolutions up to 1400 x 1050
@ 60 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.
3.2.5.1.2
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
These signals can be polarity adjusted and individually disabled in one of the two
possible states. The sync signals should power up disabled in the high state. No
composite sync or special flat panel sync support will be included.
These signals can be polarity adjusted and individually disabled in one of the two
possible states. The sync signals should power up disabled in the high state. No
composite sync or special flat panel sync support will be included.
3.2.5.2
Single Channel LVDS Port
The processor has an integrated single channel LVDS (Low Voltage Differential
Signaling) port that supports 1x18 data format. There is one LVDS transmitter channel
in the LVDS port; this channel consists of 3 data pairs and a clock pair. The channel
supports transmit clock frequency ranges from 25 MHz to 112 MHz which provides a
throughput of up to 784Mbps on each data output and up to 112 MP/s on the input.
Signaling) port that supports 1x18 data format. There is one LVDS transmitter channel
in the LVDS port; this channel consists of 3 data pairs and a clock pair. The channel
supports transmit clock frequency ranges from 25 MHz to 112 MHz which provides a
throughput of up to 784Mbps on each data output and up to 112 MP/s on the input.
3.2.5.2.1
LVDS Data Pairs and Clock Pairs
The LVDS data and clock pairs are identical buffers and differ only in the use defined for
that pair. The LVDS data pair is used to transfer pixel data as well as the LCD timing
control signals. A single clock pair is used to transfer clocking information to the LVDS
receiver. A serial pattern of 1100011 represents one cycle of the clock.
that pair. The LVDS data pair is used to transfer pixel data as well as the LCD timing
control signals. A single clock pair is used to transfer clocking information to the LVDS
receiver. A serial pattern of 1100011 represents one cycle of the clock.
There is one LVDS transmitter channel in the LVDS interface. It contains 1-clock pair
and 3-data pair of low voltage differential swing signals.
and 3-data pair of low voltage differential swing signals.
shows a pair of
LVDS signals and swing voltage.
HSYNC
VSYNC
Voltage
3.3V
Enable/Disable
Port control
Polarity Adjust
VGA or port control
Composite Sync Support
No
Special Flat Panel Sync
No
Stereo Sync
No
DDC
Voltage
External buffered to
5V
Control
Through GPIO
interface
Table 3-17.Analog Port Characteristics
Signal
Port Characteristics
Support